ÁùºÏ²ÊÖ±²¥¿ª½±

Introduction

With soaring complexity and size of chips, achieving predictable design closure has become a challenge. A multitude of coding style, structural and electrical design issues can manifest themselves as design bugs and result in design iterations, or worst still¡ªsilicon re-spins. Other tools may detect design bugs but often at late stages of design implementation, after a significant investment in time and effort has already been made. As design teams become geographically dispersed, consistency and correctness of design intent becomes a key challenge for chip integration teams. Emphasis on design reuse and IP integration requires that design elements be integrated and meet guidelines for correctness and consistency.

Features and Benefits

• Sophisticated static and dynamic analysis identifies critical design issues at RTL
• A comprehensive set of electrical rules check to ensure netlist integrity
• Includes design reuse compliance checks, such as STARC? and OpenMORE to enforce a consistent style throughout the design
• Customizable framework to capture and automate company expertise
• Integrated debug environment enables easy cross-probing among violation reports, schematic and RTL source
• The most comprehensive knowledge base of design expertise and industry best practices
• Supports Verilog, VHDL, V2K, SystemVerilog and mixed-language designs
• Tcl shell for efficient rule execution and design query
• SoC abstraction flow for faster performance and low noise