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Reduce Process Development Time and Cost

Design Technology Co-Optimization (DTCO) is a methodology that helps semiconductor fabs reduce cost and time-to-market in advanced process development. The ÁùºÏ²ÊÖ±²¥¿ª½± DTCO Solution enables the efficient evaluation and down-selection of new transistor architectures, materials and other process options using power, performance and area (PPA) design metrics.

By deploying DTCO, technology development teams develop new patterning techniques with Proteus Mask Synthesis and Sentaurus Lithography, model new materials with QuantumATK, evaluate and optimize new transistor architectures with Sentaurus TCAD and Process Explorer and extract compact models with Mystic. Design rules derived from these process options are then used to design and characterize a standard cell library with SiliconSmart and HSPICE, and to carry out block-level PPA evaluations using the ÁùºÏ²ÊÖ±²¥¿ª½± Fusion Technology physical implementation flow based on IC Compiler II, StarRC, PrimeTime and IC Validator.

Benefits of the ÁùºÏ²ÊÖ±²¥¿ª½± DTCO Solution

• Industry-proven ÁùºÏ²ÊÖ±²¥¿ª½± TCAD and Mask Synthesis tools provide accurate simulations of materials, lithography, and transistor process options before wafers are available
• Concurrent standard cell library and block-level design with Fusion Technology evaluates process options in realistic design contexts, and provides feedback to process development teams
• Variation-aware models for HSPICE simulation, StarRC parasitic extraction and PrimeTime static timing analysis (STA) accurately model the effects of variation on timing and power for highest reliability design with least over-design and design flow runtime overhead