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The ÁùºÏ²ÊÖ±²¥¿ª½± next-generation RTL design and synthesis solutions, including ÁùºÏ²ÊÖ±²¥¿ª½± RTL Architect? and ÁùºÏ²ÊÖ±²¥¿ª½± Design Compiler? NXT, are helping engineers achieve optimal PPA at all process nodes, but especially for 5nm and below.   ÁùºÏ²ÊÖ±²¥¿ª½± RTL Architect is a predictive RTL design solution that provides early predictions of the impact RTL changes will have on implementability, power, performance, area and other quality metrics. ÁùºÏ²ÊÖ±²¥¿ª½± Design Compiler NXT, the latest evolution of the ÁùºÏ²ÊÖ±²¥¿ª½± Design Compiler family of RTL Synthesis products, incorporates state-of-the-art synthesis innovations, delivering significantly faster runtimes, improved QoR, and extremely tight RC and timing correlation with ÁùºÏ²ÊÖ±²¥¿ª½± IC Compiler? II.

The Design Compiler family includes ÁùºÏ²ÊÖ±²¥¿ª½± Power Compiler, for low-power synthesis and optimization, and the ÁùºÏ²ÊÖ±²¥¿ª½± IP Library with its unequaled variety of synthesizable IP. It is also tightly linked to the ÁùºÏ²ÊÖ±²¥¿ª½± TestMAX family of test products for the fastest, most cost-effective path to high-quality manufacturing tests and working silicon and ÁùºÏ²ÊÖ±²¥¿ª½± Formality for equivalence checking. 

As an important part of the ÁùºÏ²ÊÖ±²¥¿ª½± Digital Design Family, ÁùºÏ²ÊÖ±²¥¿ª½± Fusion Compiler? is the industry's first RTL-to-GDSII solution enabling a highly-convergent, full digital implementation flow. ÁùºÏ²ÊÖ±²¥¿ª½± Fusion Compiler is built on a single, highly-scalable data-model and comprises common engines for synthesis, placement, legalization, clock-topology-creation routing, timing, and extraction. These best-in-class engines form a single, unified optimization framework that is the key enabler of ÁùºÏ²ÊÖ±²¥¿ª½± Fusion Compiler¡¯s full-flow convergence, leading QoR and enhanced time-to-results.