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Squeezed by power, performance, and area (PPA) demands, memory designs are moving into a hyper-convergent space, consisting of multiple technologies, protocols, and architectures in one highly complex, increasingly digitized design. To facilitate development of hyper-convergent memory, ÁùºÏ²ÊÖ±²¥¿ª½± provides fast technology pathfinding, design-technology co-optimization (DTCO), and early design PPA assessments using early process development kit generation flow and integration between TCAD and custom/digital design tools. This is augmented by ultra-fast conventional and machine learning-driven simulation, and ¡°digitized¡± memory design implementation flows using digital tools spanning timing characterization, digital-on-top verification, and place and route, to enable fast and accurate PPA optimization.

With every new memory protocol comes a big step up in performance and runtime. At the same time, the unique needs of different applications are driving increased customization. To scale up swiftly and meet the requirements of new protocols and unique specifications, you need faster design-to-signoff turnaround time. ÁùºÏ²ÊÖ±²¥¿ª½± can help you shift memory design left by providing faster block or chip-level simulation turnaround times, a machine learning-driven design optimization flow, faster design closure with early parasitic analysis, higher design productivity with layout reuse, and ¡°digitized¡± memory design implementation flows. You can also lower integration risks and speed time-to-market with our memory IP.?