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Complex Baseband Processing

Efficient and optimized processors increase work completed per cycle, reducing power 

• ARC HSxD: Combined CPU+DSP architecture and multicore control operations; efficient interfacing to hardware accelerators 
• ASIP Designer: Programmable, task-optimized cores/accelerators. Ultra-low power and size, high computation throughput
• ARC VPX: Wide SIMD/VLIW processor with ISA optimized for communications algorithms and machine learning

High-Speed AFE

Analog front-end delivers GHz channel bandwidth support at very low power. Modular 5G AFE supports:

• Different MIMO arrangements
• Processing of largest 5G channels and carrier aggregation
• Direct RF conversion for RFIC simplification
• Integration within SoC for lowest power and BOM cost
• High performance for processing high QAM requirements
• More than 300 designs for mobile and wireless
  

High-Performance, Trusted Interface IP

Available in 22-nm to 7-nm required for high-performance 5G designs

• MIPI CSI-2, DSI, and M-PHY offers high-speed serial interfaces between application/image processors & camera sensors
• LPPDR5/4/4X IP implements several low-power states with short exit latencies
• PCI Express 5.0/4.0 IP delivers high throughput for chip-to-chip communication
• Multi-Protocol PHYs deliver high-quality signal integrity and advanced power management capabilities for interfaces such as PCIe, CCIX, Ethernet and more

Security IP with a Hardware Root of Trust

Security protocol acceleration in a trusted environment:

• tRoot HSM provides a secure enclave in which to process sensitive data and operations for the SoC
• Security Protocol Accelerator (SPAcc) supports encryption and authentication
• High-Performance AES-XTS for Data-at-Rest encryption / decryption