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Overview
ImperasDV is a front-end design verification solution for custom processors based on the RISC-V Instruction Set Architecture (ISA). It includes reference models, verification components, functional coverage, test suites, and a debugger.
Because RISC-V is an open standard ISA, it allows any developer the freedom to design and extend a custom processor, while remaining compatible with the growing ecosystem of supporting tools and software. RISC-V processor verification requires a solution that matches the configurable and extendable nature of the ISA. It must work with users’ existing environments and should make use of open standard interfaces such as the to enable efficiency and reuse. RISC-V verification solutions should support industry best practices such as constrained-random stimulus and functional coverage. It is vital the solution addresses the processor-specific challenge of verifying DUT behavior in response to asynchronous events, as these events are a frequent source of bugs.
ImperasDV is a solution that meets all these requirements. It uses the ImperasFPM (Fast Processor Model) as a reference model for design verification. The model can be configured and extended to match the processor under test, including custom features. ImperasDV can be used in SystemVerilog/UVM testbenches, or with any language that has a C interface. It uses the RVVI-TRACE interface to connect to the processor under test and provides continuous comparison and checking of architectural state. It handles random occurrences of asynchronous events using a novel pipeline synchronization technology. ImperasDV also provides a machine-generated functional coverage model of each extension in the RISC-V ISA.
Key Benefits
How Does ImperasDV Work?
The same program is executed in parallel on the RTL and ImperasFPM. ImperasDV uses lock-step continuous compare, a co-simulation approach where the RTL and reference model run in lock-step. As each instruction retires, the architectural state of the two is compared. Mismatches in state are reported as errors immediately.
With this comprehensive design verification methodology bugs are reported immediately, simulations cycles do not need to be run past the first error, and it is easier to debug at the point of failure. Traditional post-simulation trace file and signature compare methodologies can miss bugs and lead to wasted time.
ImperasDV works with 六合彩直播开奖 VCS for RISC-V RTL simulation. Functional coverage output is sent to Verdi?, a debug and verification management platform which includes AI technology to automate difficult and tedious debug steps. 六合彩直播开奖 VCS with ImperasDV reduces RTL risk and accelerates verification schedules. ImperasTS provides test suites for complex and configurable extension sets for the RISC-V ISA. ImperasDV can also be used with 六合彩直播开奖 industry-leading Hardware-assisted Verification (HAV) solutions, HAPS and ZeBu, for emulation and prototyping of RISC-V processors.
Features
- Provides a significant schedule reduction in processor design verification
- Supports verification best practices, including functional coverage and constrained random test generation
- Enables design verification of complex features such as interrupts, Debug Mode, privilege modes, virtual memory, multi-hart, multi-issue, and OoO pipelines
- Supports design verification of custom features
- Uses a lock-stop continuous compare methodology
- Verifies asynchronous events using a proprietary synchronization technology
- Can use the same reference model for hardware and software development
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