DDR IP | Interface IP | ��ϲ�ֱ��

��ϲ�ֱ�� DDR IP ��ϲ�ֱ��

<p>��ϲ�ֱ�� offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4, DDR3/3L, DDR2, LPDDR5X/5, LPDDR4/4X, LPDDR3, LPDDR2, HBM3, HBM2E and HBM2 SDRAMs or memory modules (DIMMs). Optimized for high data bandwidth, low power and enhanced signaling features, the silicon-proven DesignWare DDR Memory Interface IP portfolio includes a choice of scalable digital controllers, an integrated hard macro or configurable PHY delivering memory system performance of up to 8.5Gbps, and verification IP.</p>

Overview

��ϲ�ֱ�� offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4, DDR3/3L, DDR2, LPDDR5X/5, LPDDR4/4X, LPDDR3, LPDDR2, HBM3, HBM2E and HBM2 SDRAMs or memory modules (DIMMs). Optimized for high data bandwidth, low power and enhanced signaling features, the silicon-proven ��ϲ�ֱ�� DDR Memory Interface IP products include a choice of scalable digital controllers with Inline Memory Encryption (IME) Security Module, an integrated hard macro or configurable PHY delivering memory system performance of up to 8.5Gbps, and verification IP.

��ϲ�ֱ��' DDR and LPDDR PHYs are supportd by ��ϲ�ֱ��' unique ��ϲ�ֱ�� DDR PHY Compiler for determining the area and power of a customer-specific configuration.

��ϲ�ֱ�� DDR5/4, LPDDR5X/5/4/4X Controllers, and Enhanced Universal DDR Memory and Protocol Controller IP feature a DFI-compliant interface, low latency and low gate count while offering high bandwidth. Optional market-specific features like AMBA CHI, AXI/4 AXI Quality of Service (QoS) and advanced Reliability, Availability and Serviceability (RAS) features allow you to match the area and capabilities of the controllers to your needs. The ��ϲ�ֱ�� Inline Memory Encryption (IME) Security Module seamlessly integrates with ��ϲ�ֱ�� DDR and LPDDR controllers to provide confidentiality and data protection.

Products

DDR5

DDR4

DDR3/3L/3U

DDR2

LPDDR5

LPDDR4

LPDDR3

LPDDR2

LPDDR/mDDR

��ϲ�ֱ�� DDR PHY	SDRAMs Supported / Maximum Data Rate	Interface to Memory Controller	Typical Application
LPDDR5/4/4X PHY	LPDDR5 / 6400 Mbps LPDDR4 / 4267 Mbps LPDDR4X / 4267 Mbps	DFI 5.0	Design in 16-nm and below that requires high-performance mobile SDRAM support up to 6400 Mbps
LPDDR4 multiPHY	LPDDR4 / 4267 Mbps LPDDR3 / 2133 Mbps DDR4 / 3200 Mbps DDR3 / 2133 Mbps DDR3L / 2133 Mbps	DFI 4.0	Design in 28-nm and below; that requires high-performance mobile SDRAM support (LPDDR4/3) up to 4267 Mbps and/or high-performance DDR4/3 support up to 3200 Mbps for small memory subsystems.
DDR5/4 PHY	DDR5 / 6400 Mbps DDR4 / 3200 Mbps	DFI 5.0	Design in 16-nm and below that requires high-performance DDR5/4 support up to 6400 Mbps
DDR4/3 PHY	DDR4 / 3200 Mbps DDR3 / 2133 Mbps DDR3L / 2133 Mbps	DFI 4.0	Design in 28-nm and below that requires high-performance DDR4/3 support up to 3200 Mbps
DDR4 multiPHY	DDR4 / 2667 Mbps DDR3 / 2133 Mbps DDR3L / 1866 Mbps LPDDR2 / 1066 Mbps LPDDR3 / 2133 Mbps	DFI 3.1	Design in 28-nm and below that requires high-performance DDR4/3 support up to 2667 Mbps and/or high-performance mobile SDRAM support (LPDDR3/2) up to 2133 Mbps.
DDR3/2 SDRAM PHY	DDR3 / 2133 Mbps DDR3L / 1600Mbps DDR2 / 1066 Mbps	DFI 2.1	Design in 40-nm that requires high-performance DDR3 up to 2133 Mbps.
DDR multiPHY	DDR3 / 1066 Mbps DDR3L / 1066Mbps DDR2 / 1066 Mbps LPDDR / 400 Mbps LPDDR2 / 1066 Mbps	DFI 2.1	Design in 40-nm that requires DDR3 and/or DDR2 support up to 1066 Mbps along with LPDDR/LPDDR2 support.
HBM3 PHY	HBM3/ 9600Mbps	DFI 5.0	Design in 5-nm and below that requires high-performance 2.5D HBM3 SDRAM support up to 9600 Mbps.
HBM2E PHY	HBM2 / 2400 Mbps HBM2E 3600 Mbps	DFI 4.0	Design in 7-nm and below that requires high-performance 2.5D HBM2/2E SDRAM support up to 3600 Mbps.