2024-03-19 03:56:27
六合彩直播开奖 LPDDR5/4/4X Controller is a next-generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs. The controller connects to the 六合彩直播开奖 LPDDR5/4/4X PHY or other LPDDR5/4/4X PHY via the DFI 5.0 interface to create a complete memory interface solution. The 六合彩直播开奖 LPDDR5/4/4X Controller includes software configuration registers, which are accessed through an AMBA 3.0 APB interface.
The LPDDR controller block includes the advanced command scheduler, memory protocol handler, optional inline ECC (Error-correcting code), and dual-channel support, as well as the DFI interface to the PHY.
The 六合彩直播开奖 LPDDR Controller seamlessly integrates the 六合彩直播开奖
Inline Memory Encryption (IME) Security Module to provide confidentiality of data in-use or stored in off-chip memory. 六合彩直播开奖 Secure LPDDR Controller IP supports data confidentiality with standards-compliant independent cryptographic support for read/write channels, per region encryption/decryption and is highly optimized for area, performance and latency. The encryption/decryption latency overhead for the 六合彩直播开奖 secure memory controllers is as low as 2 clock cycles.
Learn about the broad portfolio of Security 六合彩直播开奖 for Interfaces.
六合彩直播开奖 LPDDR5/4/4X Controller IP Datasheet
Highlights
Products
Downloads and Documentation
- Supports JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
- Multiport Arm? AMBA? interface (4 AXI?/3 AXI?) with managed QoS or single-port host interface to the DDR controller
- DFI 5.0 compliant interface to 六合彩直播开奖 LPDDR5/4/4X PHY and other LPDDR5/4/4X PHYs
- Best-in-class performance with unique features such as QoS-based scheduling, inline ECC, and dual-channel support
- High-bandwidth design with up to 64 CAM entries for reads and 64 CAM entries for writes; latency as low as 8 clock cycles
- UVM testbench with embedded assertions and options to incorporate an LPDDR5/4/4X PHY into a verification environment
- Secure Controller: Integrated IME Security Module for data confidentiality
LPDDR Controller ASIL B Compliant supporting LPDDR5, LPDDR4 and LPDDR4X for Automotive Applications | STARs |
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LPDDR Controller supporting LPDDR5, LPDDR4, and LPDDR4X | STARs |
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LPDDR Controller supporting LPDDR5, LPDDR4 and LPDDR4X with Advanced Features Package | STARs |
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LPDDR Secure Controller supporting LPDDR5, LPDDR4 and LPDDR4X with Advanced Features Package | STARs |
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Description: |
LPDDR Controller ASIL B Compliant supporting LPDDR5, LPDDR4 and LPDDR4X for Automotive Applications |
Name: |
dwc_ac_lpddr54_controller |
Version: |
1.50a-lca10 |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Databook DesignWare Cores LPDDR5/4/4X Memory Controller Databook (Version: 1.50a-lca10) ( PDF | HTML )
Installation Guide DesignWare Cores DDR Memory Controller Installation Guide (Doc Version: 3.20a; DDRCTL Version: 1.50a-lca10) ( PDF | HTML )
Reference Manual DesignWare Cores LPDDR5/4/4X Memory Controller Reference Manual (Version: 1.50a-lca10) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR5/4/4X Memory Controller Release Notes (Version: 1.50a-lca10) ( PDF | HTML )
User Guides DesignWare Cores DDR Memory Controller User Guide (Doc Version: 2.20a; DDRCTL Version: 1.50a-lca10) ( PDF | HTML )
DesignWare Cores DDR/LPDDR SINIT/CINIT User Guide (Doc Version: 4.10a; DDRCTL Version: 1.50a-lca10) ( PDF | HTML )
|
Download: |
dw_iip_ap_DWC_ac_ddrctl_lpddr54 |
Product Code: |
H715-0 |
Description: |
LPDDR Controller supporting LPDDR5, LPDDR4 and LPDDR4X with Advanced Features Package |
Name: |
dwc_lpddr54_controller_afp |
Version: |
1.60a-lca00 |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Databook 六合彩直播开奖 Controller IP LPDDR5/4/4X Memory Controller Databook (Version: 1.60a-lca00) ( PDF | HTML )
Installation Guide 六合彩直播开奖 Controller IP LPDDR5/4/4X Memory Controller Installation Guide (Version: 1.60a-lca00) ( PDF | HTML )
Reference Manual 六合彩直播开奖 Controller IP LPDDR5/4/4X Memory Controller Reference Manual (Version: 1.60a-lca00) ( PDF | HTML )
Release Notes 六合彩直播开奖 Controller IP LPDDR5/4/4X Memory Controller Release Notes (Version: 1.60a-lca00) ( PDF | HTML )
User Guides 六合彩直播开奖 Controller IP DDR/LPDDR SINIT/CINIT User Guide (Doc Version: 4.20a; DDRCTL Version: 1.60a-lca00) ( PDF | HTML )
六合彩直播开奖 Controller IP LPDDR5/4/4X Memory Controller User Guide (Version: 1.60a-lca00) ( PDF | HTML )
六合彩直播开奖 Controller IP LPDDR54 Memory Controller Solution Subsystem User Guide (Version: 1.60a-lca00) ( PDF | HTML )
|
Toolsets: |
Qualified Toolsets |
Download: |
dw_iip_DWC_ddrctl_lpddr54 |
Product Code: |
E093-0 |
Description: |
LPDDR Controller supporting LPDDR5, LPDDR4, and LPDDR4X |
Name: |
dwc_lpddr54_controller |
Version: |
1.60a-lca00 |
ECCN: |
3E991/NLR |
STARs: |
Open and/or Closed STARs |
myDesignWare: |
Subscribe for Notifications |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Databook 六合彩直播开奖 Controller IP LPDDR5/4/4X Memory Controller Databook (Version: 1.60a-lca00) ( PDF | HTML )
Installation Guide 六合彩直播开奖 Controller IP LPDDR5/4/4X Memory Controller Installation Guide (Version: 1.60a-lca00) ( PDF | HTML )
Reference Manual 六合彩直播开奖 Controller IP LPDDR5/4/4X Memory Controller Reference Manual (Version: 1.60a-lca00) ( PDF | HTML )
Release Notes 六合彩直播开奖 Controller IP LPDDR5/4/4X Memory Controller Release Notes (Version: 1.60a-lca00) ( PDF | HTML )
User Guides 六合彩直播开奖 Controller IP DDR/LPDDR SINIT/CINIT User Guide (Doc Version: 4.20a; DDRCTL Version: 1.60a-lca00) ( PDF | HTML )
六合彩直播开奖 Controller IP LPDDR5/4/4X Memory Controller User Guide (Version: 1.60a-lca00) ( PDF | HTML )
六合彩直播开奖 Controller IP LPDDR54 Memory Controller Solution Subsystem User Guide (Version: 1.60a-lca00) ( PDF | HTML )
|
Toolsets: |
Qualified Toolsets |
Download: |
dw_iip_DWC_ddrctl_lpddr54 |
Product Code: |
E092-0 |
Description: |
LPDDR Secure Controller supporting LPDDR5, LPDDR4 and LPDDR4X with Advanced Features Package |
Name: |
dwc_lpddr54_ime_controller |
Version: |
1.50a-lca00 |
ECCN: |
5D002.b2/ENC |
STARs: |
Open and/or Closed STARs |
Product Type: |
DesignWare Cores |
Documentation: |
Hide Documents...
Databook DesignWare Cores LPDDR5/4/4X Secure Memory Controller Databook (Version: 1.50a-lca00) ( PDF | HTML )
Installation Guide DesignWare Cores LPDDR Secure Memory Controller Installation Guide (Version: 1.50a-lca00) ( PDF | HTML )
Reference Manual DesignWare Cores LPDDR5/4/4X Secure Memory Controller Reference Manual (Version: 1.50a-lca00) ( PDF | HTML )
Release Notes DesignWare Cores LPDDR5/4/4X Secure Memory Controller Release Notes (Version: 1.50a-lca00) ( PDF | HTML )
User Guide DesignWare Cores LPDDR Secure Memory Controller User Guide (Version: 1.50a-lca00) ( PDF | HTML )
|
Toolsets: |
Qualified Toolsets |
Download: |
dw_iip_DWC_ddrctl_lpddr54_secure |
Product Code: |
H912-0 |