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The ÁùºÏ²ÊÖ±²¥¿ª½± ARC? HS45D and HS47D processors feature a dual-issue, 32-bit, RISC + DSP architecture for use in embedded applications where high-performance and high clock speed plus signal processing are required. The cores can be clocked at up to 1.9 GHz in 16ff processes (worst case, single core, base configuration) and offer outstanding performance delivering 3.0 DMIPS/MHz and 5.2 CoreMark/MHz with a small area footprint and low power consumption.

The processors are based on the advanced ARCv2DSP instruction set architecture (ISA) and pipeline, which provides leading performance-efficiency and code density, and more than 150 DSP instructions. For applications requiring higher performance, dual- and quad-core versions of the HS45D and HS47D cores are available.

The ARC HS45D features close coupled memory (CCM) and is optimized for use in applications where real-time, deterministic behavior is required. The HS47D is designed for high-performance embedded applications that require cache and includes all of the features of the HS45D plus support for up to 64K Level 1 (L1) instruction and data cache.

The processors are designed to be used in applications such as wireless baseband, voice/speech processing, home audio, automotive systems, and other high-end embedded applications that require signal processing.

ARC HS45D and HS47D Block Diagram

ÁùºÏ²ÊÖ±²¥¿ª½± ARC HS4xD Datasheet