The ��ϲ�ֱ�� ARC? processor portfolio offers two Memory Protection Unit (MPU) options. One is available for the ARC 600 family, the other for the ARC EM and ARC HS families. The ARC MPU is a separately licensable configuration option.

The MPU provides protection by dividing the address space into regions associated with specific attributes such as read, write, and execute. If an attempt is made to access a region for which an associated attribute is not permitted, the ARC processor raises an exception, and prevents the faulting instruction from completing. Access violations raise a protection violation exception.

The ARC architecture divides the memory into 16 equal-size regions. The MPU provides a means for defining up to 16 variable-size regions and assigning read, write, and execute attributes for each region in user and kernel modes. The number of regions is configurable and is specified by the user. Acceptable values are 1, 2, 4, 8, and 16.

The ARC MPU is added to the processor RTL using the ARChitect GUI.

Feature

ARC 600 MPU

ARC EM MPU

ARC HS MPU

Default region permissions

Separate kernel and user mode permissions

Protected access to MPU auxiliary registers

Action on protection violation

Memory error interrupt

EV_ProtV exception

Precise reporting of violations

MPUFA register

Uses EFA register

MPU_BUILD version field

0x01

0x02

Minimum region size

8 KB

2 KB

MPUIC register

Renamed MPU_ECR

MPUIC/MPU_ECR write violation code

MPUIC/PMU_ECR exception code

0x0027

0x0023

Programmable cacheability flag per region

Highlights

Programmable read, write and execute permissions
Separate Kernel and User mode Read/Write/Execute permissions
1, 2, 4, 8 or 16 memory regions, selectable at configuration time
Minimal gate count impact, scalable with user configuration
Default permissions, for all locations not covered by a defined region
Designed to coexist with other protection mechanisms, such as IP (code) protection on ARC EM and HS, and ARC Secure on ARC 600

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