六合彩直播开奖 Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial →
SpyGlass CDC
Comprehensive, Low-Noise Clock Domain Crossing Verification
Among the many verification challenges confronting system-on-chip (SoC) designers today, clock domain crossings (CDC) ranks near the top in difficulty. Today’s SoCs have dozens or sometimes even hundreds of asynchronous clock domains, making it very difficult to verify using conventional simulation or static timing analysis (STA). RTL simulation is not designed to verify metastability effects which cause data transfer issues across asynchronous clock boundaries and STA does not address asynchronous clock domains issues.
Introduction
CDC issues have become a leading cause of design errors. Such errors can add significant time and expense to the design-and-debug cycle, and may even find their way into silicon, necessitating costly respins. Besides the traditional CDC issues, Reset Domain Crossing (RDC) issues can also cause metastability in signals. Use of asynchronous resets is becoming more prevalent because of the wider use of multiphase power-up/boot sequences, etc. As a consequence, RDC issues are causing more and more design errors. (Please refer to the SpyGlass RDC Datasheet for more information about these reset domain crossing capabilities.) For both of these types of issues, SpyGlass? provides a high-powered, comprehensive solution.
Features and Benefits
- Protocol Independent Analysis, recognition of widest variety of synchronizers and auto detection of quasi-static signals resulting in the lowest number of false violations
- Architecture for scalable CDC and RDC verification
- Simple setup by automatically extracting the clock, reset and clock domains information; It can also extract the same information from existing SDC constraints providing a jump start to the users
- Comprehensive structural and functional analysis using formal based and simulation based solutions to deliver signoff quality
- Highest performance and CDC/RDC centric debug capabilities
- Hierarchical SoC flow to support IP based design methodologies to deliver quickest turnaround time for very large size SoCs
- Integrated with other SpyGlass solutions for RTL signoff for lint, constraints, DFT and power
- Low learning curve and ease of adoption