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Modern chip implementations are trending towards solutions based on assembling multiple dies in the package to increase modularity and flexibility. Such a multi-die approach also facilitates more cost-effective solutions by splitting functionality into several dies to improve yield as (monolithic) chip size approaches full reticle size.

The interface between the dies must address all the critical requirements for such a system:

• Power Efficiency. Multi-die system implementation should be as power efficient as the equivalent monolithic implementation. Die-to-die links use short-reach, low-loss channels with no significant discontinuities. The PHY architecture takes advantage of the good channel characteristics to reduce PHY complexity and save power.
• Low Latency. Partition of a server or accelerator SoC into multiple dies should not result in a non-unified memory architecture due to access to memory in different dies with significantly different latency. Die-to-die interfaces implement simplified protocols and connect directly to the chip interconnect fabric to minimize latency.
• High Bandwidth Efficiency. Advanced server, accelerator, and network switches require transfers of massive amounts of data between dies. The die-to-die interface must be able to support all the required bandwidth with a reduced die edge occupancy. Two alternatives are commonly used to achieve this goal: minimize the number of required lanes by deploying the PHY with a very high data rate per lane (up to 112 Gbps) or increase the density of the PHY by using finer bump pitch (micro-bumps) at  low data rate lanes (up to 8 Gbps/lane) that are parallelized in large numbers to achieve the required bandwidth.
• Robust Link. The die-to-die link must be error free. The interface must implement low-latency error detection and correction mechanisms robust enough to detect all errors and correct them with low latency. These mechanisms typically include an FEC and a retry protocol.

By combining multiple dies into one package, chiplets provide another way to extend Moore¡¯s law while enabling product modularity and process node optimization. Chiplets are used in compute-intensive, workload-heavy applications like high-performance computing (HPC).

There are four major use cases for die-to-die interfaces targeting applications like HPC, networking, hyperscale data center, and artificial intelligence (AI), among others:

Scale SoC

The objective is to increase compute power and create multiple SKUs for server and AI accelerators by connecting dies through virtual (die-to-die) connections, achieving tightly coupled performance across dies.

ÁùºÏ²ÊÖ±²¥¿ª½± combines a broad portfolio of die-to-die 112G USR/XSR and HBI PHY IP, controller IP, and interposer expertise to provide a comprehensive die-to-die IP solution to support die splitting, die disaggregation, compute scaling, and aggregation of functions. The SerDes-based 112G USR/XSR PHY and parallel-based 8G OpenHBI PHY are available in advanced FinFET processes. The configurable controller uses error correction mechanisms with replay and optional (FEC) to minimize bit error rate for reliable die-to-die links. It supports Arm?-specific interfaces for coherent and non-coherent data communication.