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Advanced geometry nodes such as FinFET pose significant design and manufacturing challenges that impact some implementation tools. In particular, complex multi-patterning lithography requirements involve:

• Rule-aware placement and routing to ensure the ability to color masks correctly and efficiently
• In-design physical verification throughout the flow to reduce time-consuming, uncertain iterations
• Accurate higher levels of extraction and timing analysis to allow for manufacturing variability

Advanced geometry nodes will enable designs to run at multi-GHz+ operating frequency. In order to achieve this, improved modeling, guidance, and analysis should be handled by tools with high degrees of predictability throughout the design flow. Size and performance requirements for next-generation designs require higher levels of capacity, enhanced multi-core processing for faster runtime, and an integrated design environment to maximize design productivity. ÁùºÏ²ÊÖ±²¥¿ª½±¡¯ comprehensive, foundry-certified advanced geometry solution provides the following features that help designs make it to market faster:?

• Early RTL design exploration and block feasibility analysis?
• Physical guidance from synthesis to place and route?
• Digital and custom co-design for advanced mixed-signal requirements?
• In-design physical verification with automatic detection and repair of complex design rules?
• Tightly coupled extraction and signoff capabilities with implementation tools?
• Physical ECO guidance and leakage recovery capabilities from signoff analysis

Taking advantage of the electrical characteristics of FinFETs requires addressing the challenges of complex, multi-patterning lithography. To help, ÁùºÏ²ÊÖ±²¥¿ª½± provides the industry's broadest silicon-proven FinFET-ready EDA solution spanning process development, SPICE design implementation, and IP. Other benefits of working with ÁùºÏ²ÊÖ±²¥¿ª½± for FinFET designs include:?

• Our early collaboration with foundries and academia for the development of the latest models, process development, and certification?
• Comprehensive solution addressing new challenges, such as double patterning and 3D transistors, introduced by 20nm planar and 16/14nm and below FinFET manufacturing rules with 3DIC integration?
• Minimal impact on existing methodology with transparent adoption, easing the transition to advanced process technologies?
• Complete foundry-certified solutions for IC design, implementation, and signoff for first-time-right silicon