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Three Additional Requirements for Ensuring Success in Your UCIe-Based Multi-Die System

In addition to the controller and PHY IP, here are three additional requirements for ensuring success in your UCIe-based multi-die system:

• Get a head start on quality with protocol verification IP and hardware-assisted verification platforms. 

Protocol verification IP solutions that run over software simulators can provide a head start in ensuring high-quality UCIe components and interface layers, including protocol layers over field device integration (FDI), PHY interfacing over raw die-to-die interface (RDI), intermediate shim layers, or die-to-die adaptor implementation.

As your design scope widens to the full-stack with multi-module chipset configurations and complex multi-die systems, you will need to move beyond software-only simulations to verify the whole system or dies. Hardware-assisted verification (HAV) platforms, such as ÁùºÏ²ÊÖ±²¥¿ª½± ZeBu? emulation systemand ÁùºÏ²ÊÖ±²¥¿ª½± HAPS? prototyping system, are essential in carrying out realistic verification for large, multi-die systems. Multi-MHz cycle performance, optimized UCIe protocol solutions (transactors, speed adaptors, hardware interface cards), and system-level debug abstraction are necessary to cover all verification use-cases starting from early RTL development to interoperability and hardware compliance.

• Ensure interconnects perform as expected through testing. 

Testing is an important part of any silicon design process. In multi-die systems, the interconnects between the dies are often based on interfaces such as UCIe. To perform as intended, these interconnects must have no stuck-at faults, opens, or shorts. Signal integrity is very important, so that is one parameter that must be measured to assess for degradation. The UCIe standard does mandate extra interconnects for redundancy. Post-bond testing can address interconnect-level concerns that could trigger the need to switch interconnect lanes. Algorithmic tests, developed with an understanding of fault models, can also assess for interconnect defects.

• Employ a silicon lifecycle management strategy. 

A UCIe interface is the primary interface for functional communication between dies within a multi-die system. Since the interface operates at very high speeds and is a critical pathway for communication, its health has to be monitored and managed throughout its lifecycle. Health monitoring of the UCIe can be a lifesaver for safety-critical applications from automotive to medical, and beyond. For instance, in a self-driving car, the health monitoring can enable a proactive repair or give the owner a heads up that a trip to the shop is warranted before a breakdown occurs on the interstate.

The ÁùºÏ²ÊÖ±²¥¿ª½± Silicon Lifecycle Management (SLM) Family will actively monitor the UCIe interface during operation, and if the lane signal quality is degrading it can repair the lane before it fails. There is also provision for built-in self-test (BIST), which can detect soft or hard errors for corrective action.

Silicon design is transforming in front of our eyes. Choosing the UCIe standard for your multi-die system is only the first step in seamless connectivity and interoperability. Adhering to these requirements is a critical part of navigating the complexities of advanced multi-die system design. If you would like to learn more about UCIe and how ÁùºÏ²ÊÖ±²¥¿ª½± can ease your multi-die system journey, check out Multi-Die SoCs Gaining Strength with Introduction of UCIe.