六合彩直播开奖

UCIe 2.0 - Setting the Tone for Chiplet Interoperability

Narasimha Babu G V L, Prasad Subudhi K. S, Deepak Nagaria

Aug 08, 2024 / 3 min read

Overview

The UCIe? (Universal Chiplet Interconnect Express?) released the UCIe 2.0 specification to bring efficient and scalable chiplet interconnection to the forefront of multi-die technology. In this blog we will discuss the best way to ascertain that chiplets are interoperable, and how to manage bring-up, initialization, discovery, events and messages, security and access control, as well as debug and test.

Before we dig deeper into UCIe 2.0, let us revisit the UCIe 1.1 specification that added features to cater to different application segments. (You can refer to our previous blog on UCIe 1.0 / UCIe 1.1 verification solution to understand our modular architecture for multi-chiplet verification.)

UCIe 1.1 Features

Flit mode support for streaming protocol

Benefits

Effective way for agnostic transport of any protocol

CRC and retry support for streaming mode

Enable error free transmission at UCIe transport, move burden away from higher layer

Stack mux on die-to-die adapter with options of two different protocols on multiplexer

Effective utilization of link bandwidth and flexibility for mix-match of protocols based on system needs

Asymmetric mode for streaming mode

Deviation from being agnostic as upstream / downstream port can now be specifically configured

Multi module link mode

Clarifications and detailed semantics of multi-module operation

UCIe 2.0 - Enabling Interoperability

While the UCIe 1.1 specification revision focused on key extensions for multi-vendor heterogenous systems, UCIe 2.0 is sowing seeds to define a chiplet interoperability ecosystem stack with a “System Architecture” definition, introducing provisioning manageability of System-in-Package (SiP).

Let’s explore the new features in UCIe 2.0. 

Management Transport Protocol (MTP)

MTP enables communication between management entities within a SiP management network. Management entities on this network generate and receive UCIe management transport packets, which traverse the network without modification. UCIe Memory Access protocol (UMAP) enables read and write access to memory associated with management entities with ability for access control.

UCIe Debug and Test Architecture (UDA)

UDA is architected for chiplet-level and SiP-level testing and debug. UDA uses functional sideband and/or mainband link and a functional management network for test and debug purposes.

UCIe-S Sideband only (SO) port

SO port is permitted for test/manageability purpose in a standard package. It is meant as an option for a low-speed test port that one can use at TestChip level.

x8, x4 (degraded) link width support for standard package

Capability for x8 (degraded x4) pin module is enabled for standard packages, whereas version 1.1 only supported x16 and x64 physical layer interfaces.

UCIe 3D packaging

3D packaging techniques enable chiplets to be stacked vertically. This method not only boosts performance and reduces latency but also enhances power efficiency, addressing the crucial needs of modern semiconductor designs. By adhering to UCIe standards, 3D packaging enables more compact, high-performance chip designs that can meet the demands of future applications.

In addition to Interoperability, UCIe 2.0 is paving way for defining scalable verification and validation platforms for chiplet designs.

UCIe MTP Topology

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Conclusion

The industry is rapidly deploying multi-die designs, requiring the technology to rapidly evolve in order to meet demand. UCIe 2.0 is the next step to enable a chiplet interoperability ecosystem. 六合彩直播开奖 is a leader in multi-die, contributing to the UCIe specificiation committee and providing a complete UCIe IP solution. 

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