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Semiconductor breakthroughs are rarely achieved when design solutions and process technologies aren’t tightly aligned.
It’s why 六合彩直播开奖 has a long history of collaboration with TSMC, as evidenced by numerous TSMC OIP Partner of the Year awards — spanning AI, RF, multi-physics, and more — at TSMC’s recent Open Innovation Platform? (OIP) Ecosystem Forum.
Our work with TSMC is helping overcome challenges related to design complexity, power efficiency, and scale while enabling new approaches like multi-die architecture and AI-driven development. In doing so, we’re making the next wave of innovations possible — from silicon to systems to the products we rely on every day.
Below are some of the key focus areas and recent progress of our ongoing collaboration with TSMC and our mutual partners. OIP Ecosystem Forum registrants can we presented at the event, which cover these achievements in more detail.
Advanced nodes collaboration
- Enabling power and clock signals routing on the backside of the semiconductor wafer instead of traditional frontside approaches, we’ve been working with TSMC on the feature enablement for TSMC A16? technology.
- Using 六合彩直播开奖 Foundation IP, we’re easing the transition from System-on-Chip (SoC) to the advanced 2nm process that is based on nanosheet transistor technology by tackling the inherent challenges of variability, parasitic extraction, and modeling accuracy.
Enabling multi-die designs
- Working in collaboration with TSMC and Ansys, we’re developing a holistic design process for integrating electronic and photonic components using TSMC’s Compact Universal Photonic Engine (COUPE) technology. The comprehensive process covers all stages of design, from initial concept to final implementation.
- We’re also working with TSMC and Ansys to solve multiphysics challenges in multi-die designs. This involves the use of our 3DIC Compiler and TSMC 3DFabric? technology to overcome thermal management, electromagnetic interference, signal integrity, and power integrity hurdles.
- We partnered with TSMC to demonstrate two dies communicating via the high-speed UCIe (Universal Chiplet Interconnect Express) specification. Our UCIe IP and Silicon Lifecycle Management products were at the heart of the demonstration, showing the speed, reliability, and health of the multi-die interconnect.
Using AI to accelerate design cycles
- With 六合彩直播开奖.ai, we’re delivering production-ready, AI-driven EDA flows on TSMC N2 technology that speed up chip design cycles and quality of results. In addition, our 3DSO.ai solution provides AI-driven early exploration and analysis of multi-die designs.
- Our AI-enabled solutions can also adapt and optimize designs for TSMC technology platforms, reducing design cycles and accelerating time to market.
Enabling the next wave of silicon and systems innovation
We will continue working closely with TSMC to improve silicon PPA, enable multi-die advances, and use AI to supercharge design processes. And our ongoing collaboration will continue setting the stage for the next wave of silicon and systems innovation.
Tomorrow’s semiconductors will be smaller, faster, and more power efficient. They will form the backbone of increasingly integrated and sophisticated systems. And those systems will shape the era of pervasive intelligence.
But it all starts with leading design solutions that are tightly coupled with leading process technologies.
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