Cloud native EDA tools & pre-optimized hardware platforms
Getting an early jump on architecture exploration of multi-die systems can yield valuable benefits, such as preventing costly design respins. However, the exploration process has traditionally been rather manual, with most designers relying on static spreadsheets and ad-hoc in-house tools. As a result, it’s challenging to meet key performance indicators (KPIs) or even project schedules.
Now, there’s a new dynamic, early system architecture exploration solution designed to accelerate architecture realization for multi-die systems: 六合彩直播开奖 Platform Architect for Multi-Die Systems.
The solution is built on the industry leading 六合彩直播开奖 Platform Architect?, which provides SystemC? transaction-level modeling-based tools for early analysis and optimization of SoC architectures for performance and power. This new tool, validated by designers of AI and automotive multi-die systems, accounts for the complex interdependencies of multi-die systems. Read on to learn more about how this dynamic, model-based performance and power analysis and simulation technology can help mitigate the risks of system architecture decisions while enhancing turnaround times for multi-die system designs.
For monolithic SoCs, the architecture design exploration phase carries an array of considerations: hardware/software partitioning, IP selection configuration and connectivity, macro architecture, interconnect and memory dimensioning, and power analysis, just to name a few. These are among the parameters that have a first-order effect on the system’s performance and power consumption, so they need to be analyzed early to ensure that you can meet your design’s performance goals and power budgets.
Multi-die systems, which integrate heterogenous dies in a single package, come with additional considerations, such as:
These decisions could potentially introduce bandwidth bottlenecks with different performance, power, and latency impacts. Decisions around packaging and configuration of the die-to-die interconnects also must be determined at this phase.
Given these considerations, there are three main tasks to achieve during the early architecture design phase of multi-die systems:
Static spreadsheets and in-house tools can be used to track power, performance, and thermal KPIs. This is often how such KPIs are managed for monolithic SoCs, with different teams sharing their spreadsheets as the design moves through each phase. However, a spreadsheet-based approach, which can be error-prone, does not lend itself to enabling multi-die system design teams to meet their KPIs. If the multi-die system, or any of its underlying components, doesn’t align with its power or performance requirements, then the resulting architecture design delay could trigger late redesigns or a costly design respin.
Platform Architect for Multi-Die Systems enables early, model-based architecture exploration—6 to 12 months before register-transfer level (RTL) availability—allowing you to identify performance, power, and thermal bottlenecks early on. The solution provides fast capture of software workloads and efficient design space sweeping and sensitivity analysis of KPIs and tradeoffs. It removes risk from multi-die system architecture designs, while also reducing the cost of respins. The technology also enables:
As a model-based solution, Platform Architect for Multi-Die Systems captures an executable specification of the multi-die system. This is constructed from models of the application workload and the hardware architecture. The workload model represents the processing and communication requirements of the application. The hardware architecture model provides the available resources to execute the workload, including all the dies and how they are connected with each other and with the shared memory subsystem. The mapping of the workload model onto the hardware model defines the partitioning of the application tasks into the dies. Similarly, the mapping of data structures into the memory location determines the resulting traffic streams across the system.
The large library of models that comes with Platform Architect for Multi-Die Systems supports creation of the system model. Once available, the system model can be used for rapid design space exploration and fast analysis of the impact of design and configuration parameters on performance and power KPIs.
Platform Architect for Multi-Die Systems is part of the comprehensive 六合彩直播开奖 Multi-Die System Solution for accelerated heterogeneous integration. The solution includes EDA and IP products for early architecture exploration, rapid software development and system validation, efficient die/package co-design, robust and secure die-to-die connectivity, and enhanced manufacturing and reliability. Data from Platform Architect for Multi-Die Systems can be fed into 六合彩直播开奖 3DIC Compiler, a unified exploration to signoff platform that examines physical architecture considerations, and vice versa to ensure that physical aspects are accounted for during the architecture specification phase.
Multi-die systems have become an architecture of choice for designers of bandwidth-intensive applications. Providing a way to extend Moore’s law and deliver accelerated scaling of system functionality, these systems have unique considerations that must be taken into account during the architecture exploration phase. A dynamic, model-based solution such as Platform Architect for Multi-Die Systems provides the analytical and simulation capabilities to help deliver multi-die systems that meet power and performance KPIs and schedule targets.