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ÁùºÏ²ÊÖ±²¥¿ª½± SLM SHS IP is an automated hierarchical test solution for efficiently testing SoCs or designs using multiple IP/cores, including analog/mixed-signal IP, digital logic cores and interface IP. It significantly reduces test integration time by automatically creating a hierarchical IEEE 1500 network to access and control all IP/cores at the SoC level, and increases test quality of results (QoR), including optimizing test time and power through flexible test scheduling of IP and cores. It simplifies SoC test pattern creation by using the IEEE 1500 network to port IP or core-level patterns to the SoC-level, and allows silicon debug and diagnostics by enabling the IP debug test modes from the SoC level. ÁùºÏ²ÊÖ±²¥¿ª½± SLM SHS IP is compliant with IEEE 1687, which allows re-use of embedded test instruments for system-level debug. The system¡¯s highly automated design-for-test (DFT) implementation and hierarchical IP and core-level test enables engineering teams to cut their test integration time to a matter of days and bring their designs to market faster and with lower design and test costs.

The system incorporates process and clock monitoring capabilities as part of the Measurement Unit (MU). Clock integrity is an important safety concern for automotive, aerospace and industrial applications. The ability to measure the clock frequency and duty cycle is critical requirement for these applications.