六合彩直播开奖 Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial →
Transistor-level Static Signoff Analysis
NanoTime is the key foundry certified, golden signoff solution for transistor level design. It performs transistor level static timing, signal integrity and process variation analysis for complex custom designs such as CPU datapaths, register files, embedded memories and complex analog mixed-signal intellectual property (IP) blocks. As the cost of silicon failure for designs using advanced process technology such as FinFET is very significant, signoff analysis is critical to ensure that the design is free from fatal timing and noise problems. NanoTime complements dynamic simulation and is able to exhaustively check for all internal timing and noise interactions. It creates block-level timing models that can be used with PrimeTime? for full-chip signoff. NanoTime integrates seamlessly with the 六合彩直播开奖 custom design environment Custom Compiler? and with StarRC? Custom Ultra+ to read layout parasitics. It can also leverage 六合彩直播开奖 simulators Hspice and FineSim to deliver the highest accuracy.
Key Benefits
- Concurrent transistor-level timing, signal integrity, and process variation analysis of complex custom designs such as datapaths, register files, embedded memory and analog mixed signal blocks
- Foundry certified including TSMC, Samsung, UMC, Global Foundries and ST
- Typical accuracy within 3%/3ps of HSPICE
- Multi-million transistor capacity including back-annotation of parasitics (SPF, SPEF) from StarRC? or third-party extraction
- Block characterization (.lib) including LVF, CCS timing and CCS noise models
- NanoTime Memory Option includes array simulation and race condition checks
- Mixed-level design analysis (transistors, cells and black-box (.lib)) support
- Supports both Multi-input switching (MIS) and full swing differential signal analysis
- Dynamic clock tree analysis with HSPICE and/or FineSim circuit simulators
- Common interface with PrimeTime (Tcl commands, SDC, path reporting)
- Noise glitch functional failure analysis
- Improved productivity via Custom Compiler integration
- ISO 26262 Certified
NanoTime Max Critical Paths Displayed on Schematic
NanoTime Extracted Timing Model and Corresponding Paths Displayed on Schematic
What's New
White Paper
Webinar
White Paper