ÁùºÏ²ÊÖ±²¥¿ª½±

How Does Glitch Power Work?

Glitches occur if signal timing within the paths of a combinational circuit are imbalanced, causing a race condition. This generates an unwanted signal transition, causing additional dynamic power (potentially leading to up to 40% additional dynamic power). 

Glitch power can be measured at the gate level using a timing-aware solution and power analysis tool. New technologies are available to measure glitch power using RTL or 0 delay simulation as well. 

Glitch power is a cost function of implementation tool power optimizations. Implementation uses the additional toggle generated by glitch to make better decisions to suppress these glitches or place them in such a way that minimizes their impact on EMIR.

What ÁùºÏ²ÊÖ±²¥¿ª½± Does ÁùºÏ²ÊÖ±²¥¿ª½± Offer?

ÁùºÏ²ÊÖ±²¥¿ª½± offers an end-to-end RTL-to-gate glitch power analysis and optimization solution. At RTL, PrimePower RTL can compute and report glitch per hierarchy so the instances with high glitch can be identified. It can also point to the RTL source line of code generating the highest level of glitch so designers can perform ¡°what if?¡± analysis to reduce glitch power. This is very applicable for AI and ML hardware where the amount of glitch power is high due to the number of operations. Optimizing glitch power for a tile can lead to high power savings at the SoC level.

The PrimePower solution also offers delay-/glitch-aware vector generation using RTL simulation. The product can generate an SAIF with glitch annotation (IG and TG) and a delay-aware SAIF from an RTL simulation on any given netlist (synthesis output, CTS output, place-and-route output, etc.). The SAIF or FSDB can be used during implementation (Fusion Compiler) or ECO (PrimeECO design closure system, tweaker) to do glitch-aware optimizations.

Finally, PrimePower gate-level power analysis and golden power signoff can perform glitch power analysis using 0 delay gate-level simulation or timing-aware simulation correlating closely to SPICE power numbers.