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Badge pick-up begins at 11:30. Lunch will be served, come early for a chance to eat and network before sessions begin.?

Complexity is pushing the limits of single process nodes and what monolithic designs can achieve. A multi-die approach offers much needed design flexibility. This approach, however, also comes with challenges that need to be overcome. As a leader in multi-die systems, Arm will address specific challenges related to system-level signoff including thermal, clock jitter, power, timing, workload and pre-silicon to post-silicon estimation. The session will then outline the signoff solutions that can help alleviate these challenges to reach signoff closure in this era of system design.?

Previously, signoff with GL simulation was too slow in recent projects because it takes time to generate GLS SDF FSDBs. Today we are now running with delay shift early on and using ÁùºÏ²ÊÖ±²¥¿ª½± PrimePower RTL FSDB and seeing Power Signoff level accuracy.

Full-chip level STA/Timing ECO is necessary verify timing for both internal block and inter-block timing paths. For over billion gate full-chip designs in advanced technology nodes, such as 3nm and 5nm, STA/Timing ECO job runtime and large memory consumption have a big impact on productivity. In order to overcome this large impact, we have adopted ÁùºÏ²ÊÖ±²¥¿ª½± PrimeTime HyperGrid, HyperScale for signoff STA, and ÁùºÏ²ÊÖ±²¥¿ª½± PrimeClosure for signoff ECO. We have strongly collaborated with ÁùºÏ²ÊÖ±²¥¿ª½± and achieved 2x productivity improvement in our STA/Timing ECO flow.

In this presentation, we will discuss total STA/Timing ECO total flow solution to verify and close timing violations efficiently.

Standard cell timing views are essential for design execution and timing sign-off. Design teams face weeks of delay after PDK release to begin design execution or timing impact assessment, waiting for the release of standard cell timing collaterals. Similarly in post-silicon debug, PDK usage is limited by lack of availability of library collateral.? Project Sicily developed in collaboration with ÁùºÏ²ÊÖ±²¥¿ª½± addresses this issue by reducing the wait time from weeks to hours through a ML-based solution that generates timing views based on new PDK collaterals within hours.? This new solution has been tested on multiple technology nodes and meets the certification criterion for STA, enabling shift-left on timing impact assessment on new PDKs. ?This technology accelerates every design flow that needs characterized timing views of standard cells.

A high-throughput, high-capacity clock jitter and integrity analysis, developed in collaboration with the ÁùºÏ²ÊÖ±²¥¿ª½±, is delivering SPICE-level accuracy for complex SOC designs. Designed to handle designs with billions of transistors, it provides comprehensive clock signoff checks for both fresh and aging devices across all technologies. This technology features advanced clock jitter analysis, ensuring precise clock performance. With support for configurations such as CTS, spine, and mesh, it guarantees reliable clock design and optimization, securing silicon success. This presentation will explore the successful development and deployment of this technology, showcasing its transformative impact as a framework for the future of SOC clock design and optimization. 

As modern SoC designs grow increasingly complex, obtaining precise RC parasitic data becomes crucial to ensure optimal performance and reliability. This presentation highlights advanced features in StarRC like the m-pin and gdslite flow that help in accurately capturing resistance and capacitance and help designers reduce overall design cycle times by providing strong debugging capabilities. Attendees will learn how StarRC helps resolve design issues to improve designer productivity and provide high quality results. 

Join us for a reception after the sessions to network with colleagues and presenters.??