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Human vision remains important, however, machine vision which is requiring high resolution image sensor connectivity is taking over. Such requirement is driving the trend towards up to 600-megapixel image sensors with artificial intelligence (AI) capabilities for additional use cases in various markets from mobile to automotive to internet-of-things (IoT). Mobile applications, mainly high-end smartphones, already deploy multiple high-resolution image sensors that require significantly higher bandwidth. Vision systems in automotive applications, such as ADAS and in-vehicle infotainment, are growing in complexity combining up to 30 image sensors with other sensing technologies like lidar, and radar. Additionally, automotive applications must meet all the stringent automotive functional safety, quality, reliability, and security standards as well as meet target Automotive Safety Integrity Levels (ASILs). Image sensors are also deployed in AI-enabled IoT applications with face recognition capabilities.

Embedded display innovations continue to be driven by mobile and automotive markets. Higher resolutions, 120 Hz refresh rate and foldable displays are already being deployed. Less complex IoT applications are also moving away from legacy display interfaces and leveraging the advantages of new standard camera and display interfaces.

Camera and display system-on-chips (SoCs) need interface technologies that allow efficient transmission of high volumes of data at a high rate. While MIPI camera and display interfaces are the de facto standard for mobile products, the industry is seeing their advantages in automotive, IoT and other emerging camera and display applications.

This article highlights the unique features of the MIPI CSI-2, DSI/DSI-2, D-PHY, and C-PHY interfaces, and briefly describes how designers can integrate the interfaces in their SoC designs using compliant MIPI IP.

MIPI D-PHY and C-PHY Interfaces

MIPI offers two physical layers for camera and display connectivity: D-PHY and C-PHY. D-PHY, a widely adopted standard proven in the industry for several years, offers up to 4.5 gigabits-per-second-per-lane data rates and continues to evolve. It's a source synchronous architecture, with a dedicated clock lane, and two operating modes for efficiency. MIPI D-PHY offers a high-speed mode with differential signaling for data transfer and a low-power mode with single-ended 1.2V signaling for control and handshake data, as seen in Figure 1. Version 3 of the D-PHY is expected be released soon with data rates up to 9 gigabits-per-second-per-lane. 

Figure 1: MIPI D-PHY implementation showing dedicated clock lanes next to data lanes

MIPI C-PHY, introduced in 2014, is being rapidly adopted for both camera and display applications. C-PHY enables higher bandwidth on restricted channels such as chip-on-glass, chip-on film, and chip-on-plastic.

As seen in Figure 2, the C-PHY implementation is quite unique with the 3-wires per trio and a 3-phase encoding. The mapping and encoding rules guarantee that the 3 wires work in concert without contention which helps with the clock and data recovery (CDR) implementation on the receiver and results in a significant increase of bandwidth and energy efficiency with less pins. The actual bitrate is 2.28x the signal rate since seven C-PHY wire transitions correspond to 16 bits of data.

C-PHY doesn¡¯t have a dedicated clock lane. The embedded clock eliminates clock spur emissions and enables a flexible connectivity arrangements of camera and display links.

C-PHY v1.2 goes up to 3.5 gigasymbols-per-second-per-trio. A typical application uses 3 trios which corresponds to ~24 gigabits-per-second total bandwidth. C-PHY v2.0 is also available and goes up to 6 gigasymbols-per-second-per-trio. 

Figure 2: MIPI C-PHY implementation showing single-ended drivers that eliminate the need for dedicated clock lanes 

MIPI D-PHY and C-PHY Integration

While MIPI D-PHY and C-PHY have their specific merits, their advantages extend when they are integrated. This is possible with IP that supports both C-PHY ad D-PHY since the electrical specifications are actually similar and most of the circuits can be re-used, aside from the line drivers and receivers. Both C-PHY and D-PHY can co-exist in a set of pins.

In an integrated C-PHY/D-PHY implementation, the same PHY IP can perform either in the C-PHY mode or D-PHY mode, providing a unique implementation that satisfies key requirements such as D-PHY maturity, D-PHY backward compatibility, flexibility of supporting both C-PHY and D-PHY connectivity, performance, power efficiency, and EMI reduction mainly in the C-PHY mode. 

Camera Serial Interface 2 (CSI-2) Interface

The MIPI CSI-2 interface is a vision platform for applications beyond mobile. Figure 1 shows the different versions of the CSI-2 standard and features. CSI-2 v1.x focuses more on enabling faster transmission for higher resolution, higher frame rates, and higher bits per pixel which are key requirements in mobile applications. Version 2.x adds more capabilities, relevant to other applications, including virtual channels, which identifies payloads coming from different sources. Virtual channels are important for applications like ADAS where multiple image sensors are used or any application where it is important to distinguish multiple exposures from the same sensor. Other CSI-2 features include:

• Power spectrum density (PSD) reduction capabilities bring image sensors closer to sensitive circuits. This is done with a scrambling mechanism to reduce repeated and periodic pixel sequences (combined with spread spectrum clock in the case od D-PHY)
• Reduction and Transport Efficiency (LRTE) reduces protocol latencies and enables aggregation of more sources targeting real-time perception and decision-making applications
• Differential Pulse Code Modulation (DPCM) compression reduces bandwidth while maintaining the key attributes that are relevant to machine vision algorithms
• RAW-16/20 color depth enables machine vision, real time perception applications that require high dynamic range (120+ dB)

CSI-2 v3.x adds even more capabilities such as Unified Serial Link (USL) which reduces the required number of wires and leverages LRTE to extend channel reach beyond the traditional 30 centimeters. This version also adds RAW-24 color depth for even higher dynamic range implementations for detecting brightness differences in conditions where lighting changes. Smart Region of Interest (SROI) is all about a selective transmission of the scene captured. This feature enables a significant bandwidth reduction for applications where the focus is to detect small difference, defects, or anomalies. The upcoming CSI-2 v4.x will address more use cases that require functional safety, security, and always-on capabilities.

Figure 3: Key features across the many generations of MIPI CSI-2

Display Serial Interface (DSI) Interface

MIPI DSI/DSI-2 is the de facto interface for embedded display applications. It enables two mode displays ¨C video mode and command mode. Video mode displays do not require frame buffers and the image refresh is handled by the host or SoC. All of this adds more complexity due to the required timing synchronization between the host and panel, however, the benefit is in the low-cost implementation since the panel doesn¡¯t have a frame buffer. On the other hand, command mode requires a local frame buffer on the display, making the implementation more expensive. The advantage, however, is the flexibility on how to refresh the pane. For example, command mode displays support partial update of the panel. Typically, the DSI port on the host SoC implements both video and command mode using video mode for the main display and command mode for the secondary display.  

DSI v1.x focuses more on enabling faster transmission for higher resolution, higher frame rates, and higher bits per pixel. It also supports VESA DSC to enable visually lossless compression to target high resolution displays. DSI-2 v1.1 adds power spectrum dissipation (PSD) reduction and a new VESA compression mechanism ¨C VESA VDC-M 1.1 which enables up to 5:1 compression with 6 bits per pixel. Vesa DSC1.1 enables up to 3:1 compression with 8 bits per pixel. Adding compression has many other benefits including a much simpler SoC architecture since less logic and link speed are required, helping to limit EMI, save power, and number of pins. The upcoming DSI-2 v1.2 will address use cases that require content protection and functional safety.

Figure 4: Key features across the many generations of MIPI CSI-2

Summary

Cameras and displays are used in cars, industrial and medical devices, smartphones and other mobile devices, and machine vision applications. Over the years, the required data for high resolution videos and images have increased, forcing camera and display SoCs to process more complex visual data. The MIPI Alliance offers a portfolio of camera and display interfaces that deliver differentiation for a wide range of advanced capabilities from basic connectivity to complex multiple-image sensor and display connectivity while addressing the fundamental requirements such as bandwidth, power consumption, and implementation cost.

ÁùºÏ²ÊÖ±²¥¿ª½± enables the integration of MIPI interfaces with a portfolio of silicon-proven DesignWare^? MIPI Camera and Display IP in advanced FinFET processes, supporting C-PHY, D-PHY, CSI-2, and DSI/DSI-2. The DesignWare MIPI C-PHY/D-PHY IP integrates the two MIPI interfaces together, delivers less than 1.3pJ/bit and operates at 24 Gb/s, while seamlessly interoperating with the DesignWare CSI-2 and DSI/DSI-2 Controller IP solutions. The DesignWare MIPI Controllers support the key features of the MIPI specifications. The ÁùºÏ²ÊÖ±²¥¿ª½± MIPI IP is ASIL B Ready IP developed and assessed specifically for ISO 26262 random hardware faults, which is a critical requirement for functional-safety applications. 

For more information visit ÁùºÏ²ÊÖ±²¥¿ª½± MIPI IP ÁùºÏ²ÊÖ±²¥¿ª½± web page.