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Traditional interconnects have been unable to deliver the bandwidth, latency, and power efficiency needs of hyperscale data centers and the data-intensive applications they support.

Enter CXL (Compute Express Link), an emerging standard for connecting memory to XPUs and maximizing memory resources across heterogenous devices. The latest evolution of the standard, the CXL 3.1 specification, delivers important enhancements like memory sharing, improved power efficiency, and support for network fabrics and multi-level switching.

Along with , we delivered the world¡¯s first CXL 3.1 multi-vendor interoperability demonstration at . In the demo, a Teledyne LeCroy Summit M616 Protocol Exerciser emulated a CXL host connected to a ÁùºÏ²ÊÖ±²¥¿ª½± CXL physical layer device (PHY) and controller ¡ª part of our comprehensive CXL IP solution ¡ª which served as an endpoint. In addition to marking the first time two vendor solutions have communicated over CXL 3.1 protocol, the demo showed how these connections can be made without the assistance of an interposer.

How CXL 3.1 increases memory utilization and reduces power consumption

The CXL 3.1 standard provides two key advantages for hyperscale and high-performance computing (HPC) environments. The first is cost and resource efficiency via increased memory utilization. Instead of point-to-point connections where memory is tied to specific devices (some of which invariably goes unused), CXL 3.1 allows memory to be pooled and shared across multiple network fabrics and many heterogeneous devices. This allows far greater flexibility for how resources are deployed and brings 100% memory utilization within view.

The other significant advantage is reduced power consumption, which remains a key priority for data center operators. By enabling efficient communication between the CPU and memory devices over a streamlined PCIe channel, CXL 3.1 reduces the need for additional memory channels and their associated power consumption.

Reducing integration risk with comprehensive, proven CXL IP

With a controller, PHY, security modules, and verification IP, ÁùºÏ²ÊÖ±²¥¿ª½± provides the industry¡¯s most comprehensive CXL IP solution. It supports CXL 3.1, 3.0, 2.0, 1.1, and 1.0 specifications as well as all CXL device types targeting accelerator, memory expander, and smart I/O products. And it is built on our industry-leading PCIe IP, which has helped achieve thousands of successful tapeouts over the past two decades.

This provides essential peace of mind and helps reduce integration risk when developing CXL-based solutions. And it¡¯s why our CXL 2.0 Controller IP was the first (and remains the only) such controller to make the Integrator¡¯s List for PCIe 5.0 and CXL 1.1 for both Host and Device. 

Because CXL is still an emerging standard that continues to evolve, the availability of IP-based hosts and test equipment capable of analyzing and validating the protocol in granular detail are paramount.

Both ÁùºÏ²ÊÖ±²¥¿ª½± and Teledyne LeCroy stand at the ready to help with CXL investigations and proofs of concept.