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System-on-Chip (SoC) designs continue to grow in both size and complexity in order to meet the ever-growing performance and power demands associated with modern technology. To keep up with this fast-paced evolution, the corresponding design-for-test (DFT) logic required for manufacturing tests has also become more complex. Increasing transistor density, combined with a growing mix of both internally developed and third-party IP present multiple challenges related to validating DFT connections. These include multiple power and clock domains, complex fault models, and pressure to achieve low DPPM and high coverage. Detecting and fixing these DFT connectivity issues early in the design flow is critical to ensure that there are no connectivity verification escapes occur later in the design process as these can cause ECOs close to tape-out. Furthermore, it is becoming increasingly important to keep the approach design agnostic so that the same technique can be deployed on any IP / block, including those from third party vendors. 

This ÁùºÏ²ÊÖ±²¥¿ª½± webinar explores techniques for addressing these connectivity challenges using the capabilities available in ÁùºÏ²ÊÖ±²¥¿ª½± TestMAX? Advisor. The presentation will examine the main characteristics of effective and robust connectivity checks and cover topics including basic customizable connectivity checks, the use of dynamic defined conditional connectivity macros and showcase the latest GUI analysis and debug capabilities. As well as being well suited to dealing with DFT connection challenges the tools and techniques highlighted in this webinar are also equally effective for detecting functional connectivity issues.