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Bernard Murphy is a part-time blogger and author with SemiWiki, author of ¡°The Tell-Tale Entrepreneur¡± and a co-author of the first edition of this book. He is also a content marketing advisor and serves on the board of Mother Lode Wildlife Care in the California Gold Country. Earlier he was CTO at Atrenta and has held technical contributor, management, sales and marketing roles variously at Cadence, National Semiconductor, Fairchild and Harris Semiconductor. Bernard has published over 700 articles in industry journals under his own byline. He received his BA in Physics and D. Phil in Nuclear Physics from the University of Oxford.

Manish Pandey is vice president of R&D and Fellow at ÁùºÏ²ÊÖ±²¥¿ª½±, and an Adjunct Professor at Carnegie Mellon University and a co-author of the first edition of this book. He completed his PhD in Computer Science from Carnegie Mellon University and a B. Tech. in Computer Science from the Indian Institute of Technology Kharagpur. He currently leads the R&D teams for formal and static technologies, and machine learning at ÁùºÏ²ÊÖ±²¥¿ª½±. He previously led the development of several static and formal verification technologies at Verplex and Cadence which are in widespread use in the industry. Manish has been the recipient of the IEEE Transaction in CAD Outstanding Young author award and holds over two dozen patents and refereed publications.

Dr. Rajeev Ranjan was group director of Applications Engineering at ÁùºÏ²ÊÖ±²¥¿ª½± for its flagship formal verification product, ÁùºÏ²ÊÖ±²¥¿ª½± VC Formal. Prior to ÁùºÏ²ÊÖ±²¥¿ª½±, Dr. Ranjan spent 10+ years at Jasper Design Automation in the role of Chief Technology Officer and VP of Application Engineering developing Jasper, followed by 5+ years at Cadence Design Systems in customer engagement and business development in all areas of verification. Dr. Ranjan is a long-term veteran in formal design verification, has published several papers and holds numerous patents in this area. Dr. Ranjan received his bachelor¡¯s degree from IIT Kanpur, master¡¯s degree from Urbana Champaign, and PhD from UC Berkeley. He also holds MBA degree from Wharton School of Business, University of Pennsylvania.

Sean Safarpour is group director of R&D at ÁùºÏ²ÊÖ±²¥¿ª½±, where he leads the development of VC Formal and all its Apps. Prior to this, he led the Application Engineering team for VC Formal and worked closely with customers to solve some of their most challenging verification problems with the help of formal verification. He is also a co-author of the first edition of this book. Prior to ÁùºÏ²ÊÖ±²¥¿ª½±, Sean was Director of R&D at Atrenta focused on new technology, and VP of Engineering and CTO at Vennsa Technologies, a start-up focused on automated root-cause analysis using formal techniques. Sean received his PhD from the University of Toronto where he completed his thesis entitled ¡°Formal Methods in Automated Design Debugging¡±.