ÁùºÏ²ÊÖ±²¥¿ª½±

For a Flash device used for booting, the performance factor relates not only to how fast the data can be read out of the device but also to how fast the device can be initialized by the system powering on. Automotive applications require a very fast boot time, and IoT applications prefer execution directly on the Flash device. 

Amongst the Flash devices available in the industry, the NOR Flash device is typically used to store the bootloader, as the processor can directly run this off the Flash device in what is known as eXecute In Place (XIP).

Several critical factors affect the SoC designer's selection of Flash devices, including device initialization time, XIP capability, and data reliability. If the system needs to execute code directly from Flash (i.e., instead of shadowing to RAM), NOR Flash is the ideal choice. The XIP capabilities in NOR Flash allow the system to reduce the utilization of expensive RAM. Instead of shadowing code to RAM, the processor can execute directly from a NOR Flash device. This approach can reduce the number of pins the processor needs to support the DRAM device, thus reducing PCB and overall system cost significantly. NOR Flash memory typically has a longer endurance than NAND Flash memory because it uses individual memory cells to store data. It is reliable because it utilizes individual memory cells to store data, which decreases the risk of errors affecting multiple pages. Hence, NOR Flash memories are best suited for boot code storage, firmware, and other low-density memory applications because of their reliability, endurance, high performance, and random-access capabilities.

SPI is a de-facto interface across semiconductor applications and nodes for multiple uses (Flash memory, PSRAM, Sensors, TPM interfacing, etc.). The existing SPI interface is limited to the number of IOs and the clock frequency, which has become a bottleneck for system performance improvements. 

SPI has been around without standardization for over four decades, but JEDEC has recently announced the JESD251C standard that specifies the eXpanded Serial Peripheral Interface (xSPI) for non-volatile memory devices. Along with the protocol standardization, xSPI provides improved data rate, low pin count and limited backward compatibility with legacy SPI devices. xSPI can work with a single controller and multiple target buses with source synchronous clocking. Since its standardization, xSPI adoption has increased in the Automotive, Networking, and Datacenter markets, especially for devices with expanded boot code sizes.

A versatile set of IO voltage options of 1.2V, 1.8V and 3.3V enables a wide range of support from mature to advanced process nodes. Regarding data throughput, with 400MB/s per pin on an 8-bit IO, xSPI can achieve 400MB/s, a 200% performance improvement compared to Quad-SPI (Table 1). With the XIP ability in NOR Flash applications, the instant-on display data can be processed without loading the boot code into SRAM, a critical requirement for cars with massive displays.