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Mobile DDR (LPDDR) Overview

LPDDR DRAMs provide a high-performance solution with significantly low power consumption, which is a key requirement for mobile applications such as tablets, smartphones, and automotive. Since SoCs for such applications tend to have fewer memory devices on each channel and shorter interconnects, the LPDDR DRAMs can run faster than the standard DDR DRAMs, (for example, LPDDR4/4X DRAMs run at up to 4267 Mbps and standard DDR4 DRAMs run up to 3200 Mbps), thereby providing higher performance. However, during idle conditions when the LPDDR DRAMs in such mobile devices aren¡¯t in use, they can be put in low-power states, such as deep-sleep states, or can run at lower frequencies using the dynamic frequency scaling (DFS) feature. Thus, the memory controller can opportunistically use these low-power features to reduce the overall power when the memory channel is idle.

LPDDR5 DRAMs offer additional power-savings using the dynamic voltage scaling (DVS) feature, in which the memory controller can reduce both the DRAM frequency and voltage during channel idle times. LPDDR DRAM channels are typically 16- or 32-bits wide, in contrast to the typical standard DDR DRAM channels which are 64-bit wide. As with the DRAM generations in the other two categories, every successive LPDDR generation (LPDDR5, LPDDR4/4X, LPDDR3, LPDDR2, LPDDR) targets a higher performance and lower power than its predecessor. Additionally, no two LPDDR generations are compatible with one another.

LPDDR5 Key Features

LPDDR5 DRAMs support data-rates up to 6400 Mbps and larger device sizes (2Gb to 32Gb/channel) at lower operating voltages (1.05/0.9V for VDD and 0.5/0.35V for I/O) than LPDDR4/4X DRAMs. Table 1 shows a comparison between LPDDR5 and LPDDR4 DRAMs:

Table 1: LPDDR5 vs LPDDR4/4X DRAMs

LPDDR5 DRAMs can support two core and I/O voltages through DVS: 1.05V and 0.5V, respectively, while operating at higher frequencies and 0.9V and 0.3V, respectively, while operating at lower frequencies. Hence, LPDDR5 DRAMs support DVS for both core and I/O voltages.

Other key LPDDR5 features include a new scalable clocking architecture for command/address (C/A) clock (CK) to allow easier SoC timing closure, flexible DRAM bank architecture modes to enable optimal performance depending on the traffic pattern, decision feedback equalizer (DFE) to boost the margins for the Write data at the DRAMs, Write X feature to save power, and link ECC to enhance memory channel RAS. The following sections describe each feature in detail.

New Scalable Clocking Architecture for Easier Timing Closure

The C/A CK has typically run at the same frequency as the data-strobes (DQS) in all prior LPDDR standards, up to LPDDR4/4X. Such a clocking scheme puts enormous pressure on both the DRAM C/A lanes and the SoC timing convergence, since the CK is the reference for C/A lanes on the memory channel and the memory controller in the SoC typically runs at half the CK frequency at the DDR PHY Interface in the DFI 1:2 ratio mode. For example, for an LPDDR4/4X speed of 4267 Mbps, the CK and DQS run at 2133 MHz, and the C/A has a data-rate of 2133 Mbps and controller clock runs at 1066 MHz.

Such a clocking scheme is not scalable at LPDDR5 speeds. Thus, LPDDR5 adopts a new clocking scheme, where CK runs at one fourth the data-strobe frequency at speeds higher than 3200 Mbps, and at half the data-strobe frequency at speeds under 3200 Mbps. Hence, even at 6400 Mbps, this clocking scheme requires CK to operate only at 800 MHz. This allows C/A to run slower (at 1600 Mbps, since C/A can transition at both rising and falling edges of CK rate (for example: DDR type) in LPDDR5) and hence greatly improves the margins on the C/A lanes. Similarly, a slower CK enables the SoC to not only close timing more efficiently, but also provides a higher performance, since the controller can now work at 800 MHz in DFI 1:1 ratio. Additionally, LPDDR5 does not support the traditional bi-directional data-strobe architecture, and instead introduces two uni-directional data-strobes: Write clock (WCK) for Writes and an optional Read clock (RDQS) for Reads. The system can choose to operate either strobe-less or with a single-ended strobe for Reads at lower speeds and save power, although a differential strobe (RDQS/RDQS#) becomes necessary for higher speeds.        

Single Tap DFE for Channel Robustness

Decision feedback equalizer (DFE) reduces inter-symbol interference (ISI) on the received data, hence improving the margins on the received data. ISI is caused by previously detected symbols on the current symbol being detected. LPDDR5 DRAMs will have a single-tap DFE to improve the margins for the Write data, thereby enhancing the robustness of the memory channel.

Write X for Lower Power Consumption

Write X is a power-saving feature that allows the system to transfer a specific bit pattern (such as an all-zero pattern) to contiguous memory locations without having to toggle the DQ bits on the channel.

Link ECC for Protection Against Errors Due to Channel Noise

Link ECC enables recovery of single bit transmission errors that occur on the channel. The data, along with the ECC is sent by the controller to the LPDDR5 DRAM, and upon receiving the data/ECC, the DRAM generates the ECC and checks if the ECC received is the same or not. Any single-bit errors are corrected before the data is written to the memory array. Hence, Link ECC is a powerful RAS feature at high speeds offering protection against errors due to channel noise.

Flexible Bank Architecture for Burst Length of 16 or 32 Beats

LPDDR5 DRAMs have a flexible bank architecture by supporting three modes (Bank-group mode (4 Banks, 4 Bank-groups), 8-Bank, and 16-Bank) for the user to select from, depending on their traffic pattern. The Bank-group mode is meant for speeds higher than 3200 Mbps and allows a burst-length of 16 and 32 beats. The 8-Bank mode supports all speeds with a burst length of 32 beats, and the 16-Bank mode supports speeds under 3200 Mbps with a burst length of 16 or 32 beats.

3 FSPs for Additional Power Savings

Unlike LPDDR4/4X DRAMs, which support 2 frequency-set points (FSP) for C/A and DQ, the LPDDR5 DRAMs have 3 FSPs for C/A and DQ. This allows the controller to rapidly switch across the three frequencies with minimum switch-time for optimal power savings. As explained before, DFS coupled with DVS makes LPDDR5 DRAMs an ideal choice for power-sensitive applications.