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Q2. Why is 3D Heterogeneous Integration so important to SWaP and, hence to the aerospace and defense markets?

Kenneth Larsen:

With 3D Heterogeneous Integration, it is possible to take an entire high-performance computing rack and shrink all computation, interconnect, and memory into a small package fitting in a backpack, or nose cone of a fighter, perhaps implanted one day. 

It has been more than 55 years since Moore's law came into being. We know that the geometric size of components on a chip cannot be reduced without a limit, meaning that one day, the number of transistors that can be integrated on a chip will reach the limit. We are not at the limit, but each technology shrink takes longer, at an enormous cost.

From a cost perspective splitting up a large chip into smaller chiplets, optimizing each chiplet in their most suitable technology and material, and combining them in a small semiconductor package is advantageous.  Smaller chips tend to yield better, chiplets can be reused in different applications, and with 3D Heterogeneous Integration, the various chiplets can be stacked, creating new possibilities in A&D designs.

Q3. What are the key challenges that the new 3DIC solutions must address?

Kenneth Larsen:

There are multiple concerns that 3DHI solutions need to address. In summary, they need to address (1) the computing performance and heat dissipation per unit volume, (2) the latency/bandwidth of the interconnect, (3) the environmental concerns, including power dissipation in extreme environments, and (4) application-specific capabilities like security and safety.

Regarding compute/volume, 3D packages have a significant advantage over traditional 2.5D and 2D designs due to die stacking using direct bonding and through-silicon vias bonding approaches, high-bandwidth, ultra-short latency, and incredibly power efficient bit transfers due to the proximity of the chiplets. ÁùºÏ²ÊÖ±²¥¿ª½± tools are unique (see Figure 1) because they can do multi-chip and package design together, along with system and chiplet signoff analysis. This is unlike legacy EDA solutions that start from the PCB realm.

Marc Swinnen:

Environmental concerns are a key challenge for our A&D customers who have high-performance semiconductors in very compact form-factors or that need to dissipate heat in challenging environments like space. The joint ÁùºÏ²ÊÖ±²¥¿ª½±-Ansys solutions address thermal management from chip through package to full system simulation. 

This also includes access to Multiphysics solvers like fluid dynamics simulation to establish the impact of fans and heatsinks, or mechanical solvers to predict thermo-mechanical stress and warpage of the multi-die package.

And with the ultra-high-speed signals in these advanced platforms, other physical design considerations like electromagnetic interference and coupling are absolute must-do analyses. With these joint solutions, customers get the state-of-the-art in 2.5D or 3DIC design and Multiphysics co-simulation of chip and package.

Q4. Why have Ansys and ÁùºÏ²ÊÖ±²¥¿ª½± Teamed for 3D Heterogeneous Integration design? Why not keep these efforts separate?

Kenneth Larsen:

ÁùºÏ²ÊÖ±²¥¿ª½± offers a complete chip design and 3D Heterogeneous Integration platform with a state-of-the-art 3DIC Compiler, 2.5D/3D die-to-die interface, and chiplet IP, integrated with ÁùºÏ²ÊÖ±²¥¿ª½± tools for design synthesis, verification, and silicon photonics. ÁùºÏ²ÊÖ±²¥¿ª½± teamed with Ansys which has a strong presence in Aerospace and Defense for state-of-the-art environmental and multi-physics simulation. Ansys adds environmental simulation for a broader envelope in several domains as well as quick optimization and retargeting for derivative products.