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Central Computer SoC Requirements

The new generation of automotive central compute SoCs will have common criteria, including high amounts of sensor data transported along the in-car network and high amounts of AI using the latest AI algorithms.

The high amounts of sensor data for safety critical ADAS applications, must be continuously processed in real time.  Data from sensors such as radar, lidar, ultrasonic, and camera sensors need to continuously arrive with the lowest latency.  The data traffic and protocols must not oversubscribe the in-car network wiring harness.  Most in-car networks using a combination of automotive grade Ethernet, direct connect MIPI links for image sensors, and legacy CAN networks.  Due to the amount of radar/lidar data running over automotive grade Ethernet, multiple streams of 10G Ethernet are required for the Ethernet links using the IEEE Ethernet Time Sensitive Networking (TSN) protocol.  By using the Ethernet TSN protocol, high priority safety-critical data packets can be transferred based on network policies to ensure lower priority data such as rear-seat entertainment does not interfere with safety-critical applications.  For imaging data, a high-resolution image sensor can generate over 10G of real-time uncompressed data per sensor which would overload the Ethernet network carrying the radar/lidar data.  As such, most imaging data is transported using a separate MIPI interface.  Several proprietary protocols have been developed to transfer MIPI-based imaging data in the severe channel conditions in the car.  In addition to proprietary data channels, the MIPI Alliance has developed the new 15m automotive A-PHY protocol to carry image data to central compute modules.  MIPI A-PHY is becoming more popular as an in-car data transfer protocol.

The new generation of centralized compute SoCs must execute real-time, simultaneous applications. Since multiple real-time applications are running simultaneously, the processing SoCs used in the centralized compute modules must support virtualization similar to high performance data center server processors.  Since the SoCs must support multiple real-time applications, the SW stacks for the applications need to be optimized for the new generation of RISC-V based high-performance automotive processors. Forward planning of the application SW will allow automakers to design the future software-defined vehicles (SDVs) and allow the introduction of new application-specific business models. But for the high-performance SoCs targeting zonal central computing, the processors must include specialized functionality to meet the performance necessary to run the real-time applications.

One key design feature for a centralized compute SoC is scalable heterogeneous multicore processors with up to 12 64-bit application processors integrated into the SoCs.  Enabling efficient software first development is a key goal of automotive SDV suppliers including SoC suppliers.  To establish a single source for automotive-grade RISC-V processors and enable compatible RISC-V based products and provide reference architectures, industry suppliers such as Bosch, Infineon, Nordic Semiconductor, NXP, and Qualcomm have formed a joint venture company name Quintauris. Quintauris seeks to enable the next-generation of SDV-compatible HW development by advancing the adoption of automotive RISC-V deployments.

To execute the AI algorithms required for safety critical ADAS applications along with AI base IVI applications such a Driver Monitoring Systems (DMS) and Occupant Monitoring Systems (OMS), the SoCs need additional deep learning AI accelerators.  The addition of generative AI allows the IVI suppliers to offer natural language digital assistants which place additional AI workloads for the central compute modules. OEMs are using AI for multiple applications in ADAS/HAD such as path planning, object/scene detection, and recognition and AI-based decisions making. The ADAS/HAD applications previously mentioned such as automatic emergency braking, lane keep aid, and adaptive cruise control are all AI based.  

Figure 2 shows a general example for a central compute SoC for merging ADAS and IVI applications. The discrete SoC shown on the left contains up to 12 64-bit application processors and an AI-based vision subsystem for camera-based AI applications.  In addition to the required processing performance, the SoC contains a separate ISO 26262 functional safety manager and an independent security subsystem to minimize security vulnerabilities.  A complete suite of connectivity interfaces including automotive grade Ethernet TSN provides multiple channels to connect to the SoC to the in-car zonal network, as well as to the additional point-to-point protocols such as MIPI. The central compute SoC includes PCI Express (PCIe) interface to expand the processing performance of the SoC by adding separate SoC accelerators to achieve multi-SoC performance.   PCI Express is the dominant peripheral protocol to connect multiple SoCs which adds AI algorithm accelerators to increase SoC performance.