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The demand for high performance computing, next-gen servers, and AI accelerators is growing rapidly, increasing the need for faster data processing with expanding workloads. This rising complexity creates two major challenges: manufacturability and cost. From a manufacturing perspective, these processing engines are approaching the maximum size of the reticle that the lithography machine can etch; and with a very large die size and correspondingly decreasing yield, the cost per die can increase significantly.
Gordon Moore once said, “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.” In chip design, to address the demands of increased performance, the industry is moving from system-on-chip (SoC) to system-in-package (SiP) by using wafer-level packaging.
Figure 1: Multi-die heterogeneous systems
A heterogeneous SoC entails partitioning the SoC at the IO or core level, using a modular approach with different building blocks. This offers several advantages, including supporting SoCs that are growing beyond reticle size, improving die yield, and enabling design modularity. However, a heterogeneous die introduces new challenges which include increased design complexity due to close interaction between the dies and package, supporting testability across assembly and manufacturing processes, and thermal management due to the proximity of the dies. 3D integration enables heterogeneous integration of IC chips fabricated with different technologies and materials, and thus permits the realization of integrated, sophisticated, and multifunctional microsystems that have high performance, low cost, and compact size requirements.
Emerging semiconductor applications that require the processing of massive quantities of data are driving the progress of advanced packaging. Various advanced packaging technologies, side-by-side or vertical placement, have emerged as part of the implementation of heterogeneous integration technology. 2.5D and 3D packaging have gained popularity as prominent solutions, each offering unique advantages and challenges, making them essential considerations for semiconductor manufacturers and designers.
In 2.5D packaging, two or more chips are laid side by side with an interposer connecting one die to another. The interposer acts as a bridge, connecting the individual dies and providing a high-speed communication interface, allowing greater flexibility in combining different functionalities on a single package. By stacking dies on an interposer, 2.5D packaging reduces the overall footprint of the package (compared to 2D), making it ideal for smaller and thinner devices. Interposers and bridges provide a large number of high-density BUMPs and traces, which helps in increasing bandwidth.
In 3D IC technology, chip connections are made through vertical stacking, enhancing the overall performance and functionality of the package. This allows the integration of chiplets with multiple layers and functionalities. A key trend of this integration – especially for 3D packaging technologies such as hybrid bonding – has led to an aggressive shrinking of the BUMP pitches between the chiplets and the resulting reduction of the corresponding interconnect distances and related parasitics.
Driven by the demands for greater bandwidth and advances in manufacturing processes and packaging technologies, there has been a significant change in interconnects from traditional copper uBUMP to the most advanced uBUMP using 40um pitch, scaling even further down to 10um (Figure 2).
Figure 2: Scaling of BUMP pitches (Source: status-of-the-advanced-packaging-2023, Yole Intelligence, June 2023)
In the 2.5D scenario, the connection between chips is made through Redistribution Layers (RDL) on an interposer, with the distance between chips usually in the order of 100um. As chip stacking technology advances in the 3D scenario, the use of uBUMP for vertical stacking of chips allows for direct connection between two chips, reducing the distance to less than 40um. This significantly reduces the size of the substrate. In addition, in 3D integration, the IO signals for transmission no longer need to be placed at the edge of the chip. Furthermore, by using the hybrid bond technology in a system of integrated chips (SoIC, 3D), the vertical connection between chips is even tighter. Hybrid bonding connects dies in packages using tiny copper-to-copper connections (<10um). The smaller BUMP pitch of a hybrid bond allows for thousands of IO channels in the same area, further increasing integration and performance. This advancement significantly improves data bandwidth even at lower operating frequencies (compared to 2.5D). Therefore, given this technological progress, opting for a solution based on simple digital IO such as 六合彩直播开奖 3DIO (Figure 3) not only enhances the reliability of IO circuits but also shows better quality of results in terms of area efficiency versus Serial IO.
Figure 3: Landscape of 3DIC interconnect (Source: Interconnect in the Era of 3DIC, TSMC, IEEE, 2022)
六合彩直播开奖 3DIO IP Solution (Figure 4) is specially tuned for multi-die heterogeneous integration with a versatile offering, enabling the optimal balance of power, performance and area (PPA) in 3D stacking for emerging packaging demands. Furthermore, the 3DIO IP enables faster timing closure which is a critical challenge in die-to-die integration.
Figure 4: 六合彩直播开奖 3DIO IP Solution is architected to support 2.5D, 3D and SoIC packages
六合彩直播开奖 3DIO IP Solution offering comprises the following:
Figure 5: 六合彩直播开奖 Synchronous 3DIO PHY view (Source: Synchronous 3DIO PHY crossectional view)
With the advancements in packaging technologies and increased density of interconnects, there is a significant rise in the IO channels for a given die area. The corresponding decrease in IO channel length increases performance but gives rise to the need for a more streamlined interface. 六合彩直播开奖 3DIO IP Solution offers versatile solutions for customers to implement tunable, integrated multi-die design structures. The optimal area of the 六合彩直播开奖 3DIO IP Solution offering is carefully designed to be within the BUMP, providing significant advantages in implementation and signal routing. In 3D stacking technologies, a source synchronous clock design for signal transmission can help customers achieve a lower BER and ease timing closure. 六合彩直播开奖 3DIO IP Solution is tailored for multi-die integration, enabling customers to create efficient chip designs with faster time to market, accelerated with 六合彩直播开奖 3DIC Compiler to ease integration and provide optimized PPA for a given technology. In addition to the 3DIO, 六合彩直播开奖 Multi-Die Solution includes UCIe IP and HBM3 IP.
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