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SNUG 中国 2018
SNUG 2018 论文集
技术委员会获奖论文（winners list）
一等奖
Reduce MBIST Area Using Shared Wrapper
二等奖
Useful Skew Enhancement for Timing Closure with IC Complier II
Using VC Formal to Do DFT Clock Verification
叁等奖
RTL Improvement for Placement and Routing
Using VC-APPs to Boost Verification and Debug Efficiency
入围论文
A Synthesized and Consistent Clock Management Solution Covering Full Pre-silicon Steps
Analysis X Source by Using SpyGlass DFT
Benefit from HyperScale Flow at Timing-closure Stage
Block Level Clock Tree Improvement
Hierarchical SOC Design Implemented by ICC II
Implementation of H-tree Clock Structure in Module with ICC II
Improving ATPG Efficiency with SpyGlass DFT in Customerized Flow
Improving Timing Convergence between ICC II and PrimeTime for 7nm design Signoff
Latch Array Implementation with Relative Placement in IC Compiler II
Using VC Formal to Check SOC Level Connections and Coverage Analyze
SNUG 2018 上海 各论坛演讲资料分享：
1. Mobile Computing & High Performance Computing
2. IoT & Low Power
3. Advanced Modeling & Manufacturing
4. Automotive
5. Machine Learning
SNUG 2018 北京 各论坛演讲资料分享：
1. Mobile Computing & High Performance Computing
2. IoT & Low Power
3. Advanced Modeling & Manufacturing