The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general-purpose accelerators, memory expanders, and smart I/O devices requiring high performance, heterogeneous computing for data-intensive workloads.
The 六合彩直播开奖 CXL 3.x Integrity and Data Encryption (IDE) Security IP Module provides confidentiality, integrity, and replay protection for flow control units (FLITs) in the case of CXL.cache and CXL.mem protocols, and for FLITs and Transaction Layer Packets (TLP) in the case of CXL.io.
The Security Module implements the IDE specification as defined for CXL 3.x which also references PCI Express 6.x IDE specification for the CXL.io protocol. The 六合彩直播开奖 CXL 3.x IDE Security Module integrates seamlessly with the 六合彩直播开奖 CXL controllers to accelerate SoC integration.
The 六合彩直播开奖 CXL 3.x IDE Security Module provides full-duplex .cache/.mem/.io support with efficient encryption/decryption and authentication of FLITs and TLPs, based on optimized low latency AES-GCM cryptographic cores, that are specially developed for optimal area, performance, and latency implementations.
Learn about the broad portfolio of Security 六合彩直播开奖 for Interfaces.
六合彩直播开奖 IDE Secure Module for CXL 3.x Datasheet
Description: | CXL 3.0 Integrity and Data Encryption Security Module |
Name: | dwc_cxl_3_ide_security_module |
Version: | 2.13a |
ECCN: | 5D002.b2/ENC |
STARs: | Open and/or Closed STARs |
Product Type: | DesignWare Cores |
Documentation: | |
Toolsets: | Qualified Toolsets |
Download: | dw_iip_DWC_cxl_ide |
Product Code: | H314-0 |