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ÁùºÏ²ÊÖ±²¥¿ª½± UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI, and networking applications. The PHY¡¯s flexible architecture supports standard and advanced package technologies and allows up to 12.9Tbps/mm of data to travel at data rates up to 40Gbps. It supports widely used AMBA protocols such as AXI and CHI C2C in streaming mode and standards-based protocols such as PCI Express and CXL. The IP offers maximum performance with low BER, minimum latency, and implementation flexibility. ÁùºÏ²ÊÖ±²¥¿ª½± UCIe PHY IP delivers high energy efficiency with an optimized architecture using a single reference clock feature, low-voltage signaling, and hardware-based initialization. The mission mode integrated signal integrity monitors and comprehensive test and repair capabilities ensure die, die-to-die, and multi-die package health from in-design to in-field. Robust die-to-die link operation is ensured with embedded training and calibration algorithms. The PHY is compliant with the latest release of the UCIe specification, ensuring successful interoperability between heterogeneous dies. ÁùºÏ²ÊÖ±²¥¿ª½± UCIe PHY IP along with ÁùºÏ²ÊÖ±²¥¿ª½± Controller IP and Verification IP deliver a complete solution for die-to-die connectivity in multi-die packages.

ÁùºÏ²ÊÖ±²¥¿ª½± UCIe PHY IP Datasheet