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Using Formal Datapath Validation to Verify ÁùºÏ²ÊÖ±²¥¿ª½± IP

ÁùºÏ²ÊÖ±²¥¿ª½± VC Formal DPV is not only used by leading companies designing CPU, GPU, AI/ML chips, it has also been used by ÁùºÏ²ÊÖ±²¥¿ª½±¡¯ own ÁùºÏ²ÊÖ±²¥¿ª½± Group to verify IP blocks and foundation cores since 2006. It is truly the golden standard of datapath verification tool in the industry.

Helping Management Understand Formal Progress Through Performance Indicators

Amber Telfer, Principal Engineer at Microsoft, discusses what formal performance indicators are and how they help management understand the progress made in your formal verification projects. Watch this video to learn how to use performance indicators to make your own formal work count.

Scaling Up Formal Unreachability Analysis for Coverage Closure

Luv Sampat, Sr. Formal Verification Engineer at Qualcomm, discusses why it is important to reach 100% coverage closure and how ÁùºÏ²ÊÖ±²¥¿ª½± VC Formal¡¯s FCA auto-scale technology has helped him solve coverage closure challenges.

RISC-V Formal Verification and Clock Gating Signoff

Shaun Feng, Senior Principle Engineer at SiFive, explains what clock gating signoff means, why it is important, how designers can help, and whether RISC-V formal verification is different from other CPU formal verification methodologies.

HECTOR and VC Formal DPV Past, Present, and Future

VC Formal DPV, with HECTOR technology, has helped verification engineers find the toughest bugs in their datapath designs for over a decade. Learn about the history of HECTOR from Alfred Koelbl, ÁùºÏ²ÊÖ±²¥¿ª½± scientist, and architect of the technology.

Discussing Formal Deployment, Architectural Verification, and Building a Formal Team

Achutha KiranKumar V M, Intel Fellow, shares his insights on why formal adoption has accelerated in the last 5 years, why architectural verification is important in left shift project cycle, and how to build a formal team from the ground up.