Scaling Processor Performance and Safety to Meet Requirements for Next-Generation Safety-Critical Automotive Designs
Scaling Processor Performance and Safety to Meet Requirements for Next-Generation Safety-Critical Automotive Designs
This white paper proposes a state-of-the-art processor architecture targeting automotive safety systems that meets the requirements of such active safety systems delivering the required processing performance, providing the highest automotive safety integrity level (ASIL) while also significantly contributing to a reduction in overall cost of the systems through the use of artificial neural networks (ANNs). The use of ANNs executing on the processor architecture provides the ability to replace physical sensors with virtual sensors. This processor architecture is based on a safety enabled vector DSP processor delivering up to 25X performance requirements over standard RISC cores. The state-of-the-art architecture combination of DSP parallelism and safety mechanisms avoids the need for brute force lockstep to achieve the required ASIL. It also shows the justification for the increased safety requirements for applications needed in L2+ autonomous vehicles by analyzing the performance requirements of two example automotive use cases, radar and electric vehicles/eMobility.
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