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As we prepare for a digital-first world, we aspire for smart technologies to do everything ¡ª vehicles to drive themselves, appliances to complete our tasks, gadgets to interpret our needs, and devices to match the capabilities of our imaginations. As innovators continue to dream, invent, and build sophisticated tools to enable these breakthroughs, the success of the devices and the underlying chip design powering these technologies relies heavily on optimal power consumption.

But this hasn¡¯t always been the case. Back when many portable consumer electronics consisted of lower powered devices such as watches, Walkman players, and calculators, energy consumption was a low priority in comparison to chip speed (performance) and size (area). However, with the ubiquitous rise in power ¡ª and data-hungry devices such as smartphones, laptops, smart home devices, and tablets as well as large appliances, server farms, and IoT machinery ¡ª the need for a solid power optimization strategy has moved up the value chain across applications unlike ever before.

As chip design sizes increase, so does the total power consumption driving its operations. To meet with the increasing intelligence and power-management flow required by these applications, system on chip (SoC) designers and verification engineers need comprehensive solutions that leverage low-power design techniques to enable support for fine-grained power management.

Over the years, the Unified Power Format (UPF) standard, intended for specifying and verifying power intent of integrated circuit (IC) designs, has advanced and created a wide range of opportunities for the electronics industry to develop power management techniques. However, for low-power cells like hard macro, RAM cell, or PAD, the connectivity of low-power control signals remains ambiguous.

Read on to learn about the basics of UPF, its importance in the power landscape, how to expand low-power signoff with custom mechanisms and take power-managed designs to the next level.

Expanding Low-Power Signoff: UPF and Beyond

Typically, once the initial steps for low-power design are conducted ¡ª selection of low-power components, system simulations, UPF, and register transfer level (RTL) coding ¡ª designers move to the verification phase, which requires a comprehensive toolkit with several capabilities. The initial step is static power verification and exploration, ensuring the inputs to the design flow (RTL, UPF, and SDC) are structurally and syntactically correct. Designers need to conduct Lint and CDC checks to make sure the RTL is clean. UPF and SDC checks can be then conducted concurrently with the RTL checks ¡ª but a tool that can run these checks and perform power analysis to ensure the design functions properly is key.

Software-driven power analysis comes next. For emulation-based low power flows, it is important for chip designers to ensure that peak windows for the design¡¯s power profile are used and leveraged to generate waveforms that estimate power.

The power implementation phase includes several steps for power estimation, logic synthesis, and generating a netlist. Once the checks are complete, the final physical components are placed and routed. During the final step ¨C signoff ¨C designers must ensure that the connections and changes made to the netlist and UPF are consistent and clean, and the power intent is preserved.

Over the years, UPF has grown by incorporating several advanced capabilities. These range from power-intent specification process simplification to power-management flow alignment requirements of IP-based SoC designs. Verification of low power control signals by leveraging control signal connectivity of typical low-power cells such as isolation, retention, and coarse grain power switch within UPF.

However, for certain low-power cells, such as hard RAM and hard macro, the connectivity of low-power control signals is unclear. This makes verification a complex and manual process often leading to costly bug escapes. Simulation can identify some of these issues but is contingent on a robust simulation environment and corresponding debug capabilities. It also occurs very late in the verification cycle increasing the cost of the verification.

Cases where UPF does not have a way to define specification:

• While UPF is extensive, the control signal connectivity for low-power cells such as RAM and hard macros remains undefined. Chips are often designed with several RAM cells, and their architecture within the chip is critical to define memory controls and enable low-power optimization features such as sleep and retention enablers. During the design process, engineers frequently rely on simulation to find connectivity issues and other power-related bugs. However, simulations take days and are typically time-intensive procedures.
• Hard macros present a similar problem. They are often several blocks built into the chip¡¯s design and internally isolated. UPF doesn¡¯t provide checks for internal isolation control or polarity for internally isolated pins.
• In addition, it is also important to verify an IP-level control signal¡¯s connectivity to the correct SoC signal when the IP is integrated into the SoC to ensure accurate verification at the SoC level. Currently, UPF does not have a mechanism to define the specification for this connectivity.
• Power state table (PST) dependent isolation enable checks is another area where the Low Power Architect usually defines how the isolation enable signal and its sense are related to a supply. If isolation enable becomes active or inactive in the wrong power state table, then it can propagate corruption or clamp value towards power-on logic and that may not be intended in a PST.

To support the increasing demands of advanced power management from many of today¡¯s electronic products, it is critical to have a comprehensive low-power verification tool that validates the final design functions accurately and can accomplish all of the phases for UPF and RTL checks, power analysis, and signoff.

For more information on UPF and pre-empting low-power issues, watch this webinar on using predictive analysis to detect critical low-power bugs early in the design cycle.